| Message ID | 20170823060856.9387-8-Zhiqiang.Hou@nxp.com |
|---|---|
| State | Changes Requested |
| Headers | show |
On Wed, Aug 23, 2017 at 02:08:54PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Use the accessors instead accessing the DBI read-only write enable > register directly. This patch and the previous one (that added dw_pcie_dbi_ro_wr_en()) should be squashed together. That way it's obvious that the new code here is equivalent to the old code > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > Acked-By: Joao Pinto <jpinto@synopsys.com> > --- > V4: > - no change > > drivers/pci/dwc/pci-layerscape.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c > index 44a603db217a..0c1330fce01d 100644 > --- a/drivers/pci/dwc/pci-layerscape.c > +++ b/drivers/pci/dwc/pci-layerscape.c > @@ -33,7 +33,6 @@ > > /* PEX Internal Configuration Registers */ > #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ > -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ > > #define PCIE_IATU_NUM 6 > > @@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp) > */ > ls_pcie_disable_outbound_atus(pcie); > > - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); > + dw_pcie_dbi_ro_wr_en(pci); > ls_pcie_fix_class(pcie); > ls_pcie_clear_multifunction(pcie); > - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); > + dw_pcie_dbi_ro_wr_dis(pci); > > ls_pcie_drop_msg_tlp(pcie); > > -- > 2.14.1 >
Hi Bjorn, Thanks a lot for your comments! > -----Original Message----- > From: Bjorn Helgaas [mailto:helgaas@kernel.org] > Sent: 2017年8月25日 1:15 > To: Z.q. Hou <zhiqiang.hou@nxp.com> > Cc: linux-pci@vger.kernel.org; bhelgaas@google.com; > jingoohan1@gmail.com; Joao.Pinto@synopsys.com; M.h. Lian > <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy Zang > <roy.zang@nxp.com>; svarbanov@mm-sol.com; niklas.cassel@axis.com; > jesper.nilsson@axis.com > Subject: Re: [PATCHv4 7/9] PCI: layerscape: use accessors to enable/disable > DBI RO registers' write permission > > On Wed, Aug 23, 2017 at 02:08:54PM +0800, Zhiqiang Hou wrote: > > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > > > Use the accessors instead accessing the DBI read-only write enable > > register directly. > > This patch and the previous one (that added dw_pcie_dbi_ro_wr_en()) should > be squashed together. That way it's obvious that the new code here is > equivalent to the old code Thanks for your suggestion, will merge them together. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Acked-By: Joao Pinto <jpinto@synopsys.com> > > --- > > V4: > > - no change > > > > drivers/pci/dwc/pci-layerscape.c | 5 ++--- > > 1 file changed, 2 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/pci/dwc/pci-layerscape.c > > b/drivers/pci/dwc/pci-layerscape.c > > index 44a603db217a..0c1330fce01d 100644 > > --- a/drivers/pci/dwc/pci-layerscape.c > > +++ b/drivers/pci/dwc/pci-layerscape.c > > @@ -33,7 +33,6 @@ > > > > /* PEX Internal Configuration Registers */ > > #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask > Register1 */ > > -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable > Register */ > > > > #define PCIE_IATU_NUM 6 > > > > @@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp) > > */ > > ls_pcie_disable_outbound_atus(pcie); > > > > - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); > > + dw_pcie_dbi_ro_wr_en(pci); > > ls_pcie_fix_class(pcie); > > ls_pcie_clear_multifunction(pcie); > > - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); > > + dw_pcie_dbi_ro_wr_dis(pci); > > > > ls_pcie_drop_msg_tlp(pcie); > > > > -- > > 2.14.1 > > Thanks, Zhiqiang
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c index 44a603db217a..0c1330fce01d 100644 --- a/drivers/pci/dwc/pci-layerscape.c +++ b/drivers/pci/dwc/pci-layerscape.c @@ -33,7 +33,6 @@ /* PEX Internal Configuration Registers */ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ -#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ #define PCIE_IATU_NUM 6 @@ -145,10 +144,10 @@ static int ls_pcie_host_init(struct pcie_port *pp) */ ls_pcie_disable_outbound_atus(pcie); - iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN); + dw_pcie_dbi_ro_wr_en(pci); ls_pcie_fix_class(pcie); ls_pcie_clear_multifunction(pcie); - iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN); + dw_pcie_dbi_ro_wr_dis(pci); ls_pcie_drop_msg_tlp(pcie);