| Message ID | 1503387220-39013-1-git-send-email-ying.zhang22455@nxp.com |
|---|---|
| State | Changes Requested |
| Delegated to: | York Sun |
| Headers | show |
The subject doesn't represent your change. Please revise. On 08/22/2017 03:47 AM, ying.zhang22455@nxp.com wrote: > From: Zhang Ying-22455 <ying.zhang22455@nxp.com> > > The SP805-WDT module on LS1088A requires configuration of PMU's > PCTBENR register to enable watchdog counter decrement and reset > signal generation. The watchdog clock needs to be enabled first. > > Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> > --- > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > index c6fede3..ea983e4 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > @@ -531,7 +531,7 @@ int timer_init(void) > #ifdef CONFIG_FSL_LSCH3 > u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; > #endif > -#ifdef CONFIG_ARCH_LS2080A > +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS1088A) NAK. Do not revert back to CONFIG_LS2080A. York
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c6fede3..ea983e4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -531,7 +531,7 @@ int timer_init(void) #ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; #endif -#ifdef CONFIG_ARCH_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS1088A) u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET; u32 svr_dev_id; #endif @@ -550,7 +550,7 @@ int timer_init(void) out_le32(cltbenr, 0xf); #endif -#ifdef CONFIG_ARCH_LS2080A +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS1088A) /* * In certain Layerscape SoCs, the clock for each core's * has an enable bit in the PMU Physical Core Time Base Enable