Patchwork [U-Boot] powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020

login
register
mail settings
Submitter Kumar Gala
Date Jan. 25, 2011, 6:47 p.m.
Message ID <1295981224-16465-1-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/80397/
State Accepted
Commit fbee0f7f09e94c0967ac118d41388c3edb0c226d
Delegated to: Kumar Gala
Headers show

Comments

Kumar Gala - Jan. 25, 2011, 6:47 p.m.
Specify the number of DDR controllers, number of frame managers, number
of 1g and 10g ports.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 arch/powerpc/include/asm/config_mpc85xx.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)
Kumar Gala - Feb. 1, 2011, 4:44 a.m.
On Jan 25, 2011, at 12:47 PM, Kumar Gala wrote:

> Specify the number of DDR controllers, number of frame managers, number
> of 1g and 10g ports.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/include/asm/config_mpc85xx.h |   15 +++++++++++++++
> 1 files changed, 15 insertions(+), 0 deletions(-)

applied to 85xx next

- k

Patch

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index a78086b..0f83d15 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -140,11 +140,18 @@ 
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_NUM_DDR_CONTROLLERS	1
 
 #elif defined(CONFIG_PPC_P3041)
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	1
 
 #elif defined(CONFIG_PPC_P4040)
 #define CONFIG_MAX_CPUS			4
@@ -176,11 +183,19 @@ 
 #define CONFIG_MAX_CPUS			1
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	1
 
 #elif defined(CONFIG_PPC_P5020)
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	2
 
 #else
 #error Processor type not defined for this platform