Patchwork [ARM] Fix PR44392 on the 4.5 branch.

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Submitter Ramana Radhakrishnan
Date Jan. 25, 2011, 7:18 a.m.
Message ID <AANLkTi=Z3-mLte7OB6HMTXqFzPVjW2f990BHKyr=92cd@mail.gmail.com>
Download mbox | patch
Permalink /patch/80330/
State New
Headers show

Comments

Ramana Radhakrishnan - Jan. 25, 2011, 7:18 a.m.
Hi,

This is a regression fix for PR44392 on the branch which seems to have
dropped between the cracks . Regression tested on qemu with no
regressions.

Backported and committed to the 4.5 branch.

Ramana

2011-01-21  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	Backport from mainline.
	2010-09-08  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	PR target/44392
	* config/arm/arm.md (bswapsi2): Handle condition correctly
	for armv6 and optimize_size.
Richard Henderson - Feb. 6, 2011, 11:35 p.m.
On 01/24/2011 11:18 PM, Ramana Radhakrishnan wrote:
> +"TARGET_EITHER && (arm_arch6 || !optimize_size)"

There ought not be bare references to optimize_size in
the backend; only to optimize_insn_for_{size,speed}_p.

In this way you properly handle cold basic blocks, 
which are automatically optimized for space.


r~

Patch

Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md	(revision 169182)
+++ gcc/config/arm/arm.md	(working copy)
@@ -11273,34 +11273,29 @@ 
 (define_expand "bswapsi2"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
   	(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
-"TARGET_EITHER"
+"TARGET_EITHER && (arm_arch6 || !optimize_size)"
 "
-  if (!arm_arch6)
-    {
-      if (!optimize_size)
-	{
-	  rtx op2 = gen_reg_rtx (SImode);
-	  rtx op3 = gen_reg_rtx (SImode);
+    if (!arm_arch6)
+      {
+	rtx op2 = gen_reg_rtx (SImode);
+	rtx op3 = gen_reg_rtx (SImode);
 
-	  if (TARGET_THUMB)
-	    {
-	      rtx op4 = gen_reg_rtx (SImode);
-	      rtx op5 = gen_reg_rtx (SImode);
+	if (TARGET_THUMB)
+	  {
+	    rtx op4 = gen_reg_rtx (SImode);
+	    rtx op5 = gen_reg_rtx (SImode);
 
-	      emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
-					       op2, op3, op4, op5));
-	    }
-	  else
-	    {
-	      emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
-					     op2, op3));
-	    }
+	    emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
+					     op2, op3, op4, op5));
+	  }
+	else
+	  {
+	    emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
+					   op2, op3));
+	  }
 
-	  DONE;
-	}
-      else
-	FAIL;
-    }
+	DONE;
+      }
   "
 )