Patchwork [ARM] PR47246, VFP index range on Thumb-2

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Submitter Chung-Lin Tang
Date Jan. 25, 2011, 7:17 a.m.
Message ID <4D3E78F1.6020606@codesourcery.com>
Download mbox | patch
Permalink /patch/80329/
State New
Headers show

Comments

Chung-Lin Tang - Jan. 25, 2011, 7:17 a.m.
On 2011/1/25 下午 03:03, Chung-Lin Tang wrote:
> Hi,
> This fixes a condition I overlooked in a prior patch. The allowed
> Thumb-2 load/store index range for core registers is -256--4096
> exclusive, while the coprocessor range is still -1024--1024 like ARM
> mode. The valid intersection is then -256--1024.
> 
> This actually relates to the problem of having different valid memory
> addresses for the same machine mode when load/storing to different
> register classes (here SF/DF modes stored in both GPR and FPU regs, with
> differing index ranges), which does not seem to be an easy problem
> within GCC.
> 
> So here's the conservative patch, again tested without regressions.  It
> corrects other coprocessor cases (FPA, Maverick) together, which should
> be correct (not that I've seen Thumb-2 implementations with them)
> 
> Okay for trunk?

Forgot to attach patch :P
Here it is:

2011-01-25  Chung-Lin Tang  <cltang@codesourcery.com>

        * config/arm/arm.c (thumb2_legitimate_index_p): Change the
        lower bound of the allowed Thumb-2 coprocessor load/store
        index range to -256. Add explaining comment.
Richard Earnshaw - Jan. 25, 2011, 9:42 a.m.
On Tue, 2011-01-25 at 15:17 +0800, Chung-Lin Tang wrote:
> On 2011/1/25 下午 03:03, Chung-Lin Tang wrote:
> > Hi,
> > This fixes a condition I overlooked in a prior patch. The allowed
> > Thumb-2 load/store index range for core registers is -256--4096
> > exclusive, while the coprocessor range is still -1024--1024 like ARM
> > mode. The valid intersection is then -256--1024.
> > 
> > This actually relates to the problem of having different valid memory
> > addresses for the same machine mode when load/storing to different
> > register classes (here SF/DF modes stored in both GPR and FPU regs, with
> > differing index ranges), which does not seem to be an easy problem
> > within GCC.
> > 
> > So here's the conservative patch, again tested without regressions.  It
> > corrects other coprocessor cases (FPA, Maverick) together, which should
> > be correct (not that I've seen Thumb-2 implementations with them)
> > 
> > Okay for trunk?
> 
> Forgot to attach patch :P
> Here it is:
> 
> 2011-01-25  Chung-Lin Tang  <cltang@codesourcery.com>
> 
>         * config/arm/arm.c (thumb2_legitimate_index_p): Change the
>         lower bound of the allowed Thumb-2 coprocessor load/store
>         index range to -256. Add explaining comment.

GCC should be able to do better than this, but I agree that this is the
right patch for this phase in the development cycle.

OK.

R.

Patch

Index: config/arm/arm.c
===================================================================
--- config/arm/arm.c	(revision 169191)
+++ config/arm/arm.c	(working copy)
@@ -5786,7 +5786,11 @@ 
       && (mode == SFmode || mode == DFmode
 	  || (TARGET_MAVERICK && mode == DImode)))
     return (code == CONST_INT && INTVAL (index) < 1024
-	    && INTVAL (index) > -1024
+	    /* Thumb-2 allows only > -256 index range for it's core register
+	       load/stores. Since we allow SF/DF in core registers, we have
+	       to use the intersection between -256~4096 (core) and -1024~1024
+	       (coprocessor).  */
+	    && INTVAL (index) > -256
 	    && (INTVAL (index) & 3) == 0);
 
   if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))