@@ -56,6 +56,8 @@ config ARCH_LS1088A
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_EC1
+ select SYS_FSL_EC2
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
@@ -63,6 +65,7 @@ config ARCH_LS1088A
select SYS_FSL_ERRATUM_A008850
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_DDR4
+ select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
@@ -405,6 +408,18 @@ config RESV_RAM
be at the high end of physical memory. The reserve RAM may be
excluded from memory bank(s) passed to OS, or marked as reserved.
+config SYS_FSL_EC1
+ bool
+ help
+ Ethernet controller 1, this is connected to MAC3.
+ Provides DPAA2 capabilities
+
+config SYS_FSL_EC2
+ bool
+ help
+ Ethernet controller 2, this is connected to MAC4.
+ Provides DPAA2 capabilities
+
config SYS_FSL_ERRATUM_A008336
bool
@@ -429,6 +444,12 @@ config SYS_FSL_ERRATUM_A009660
config SYS_FSL_ERRATUM_A009929
bool
+
+config SYS_FSL_HAS_RGMII
+ bool
+ depends on SYS_FSL_EC1 || SYS_FSL_EC2
+
+
config SYS_MC_RSV_MEM_ALIGN
hex "Management Complex reserved memory alignment"
depends on RESV_RAM
@@ -517,6 +517,10 @@ int arch_early_init_r(void)
printf("Did not wake secondary cores\n");
}
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+ fsl_rgmii_init();
+#endif
+
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
@@ -159,6 +159,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
int serdes_get_number(int serdes, int cfg);
+void fsl_rgmii_init(void);
#ifdef CONFIG_FSL_LSCH2
const char *serdes_clock_to_string(u32 clock);
@@ -247,6 +247,12 @@ struct ccsr_gur {
#define FSL_CHASSIS3_SRDS1_REGSR 29
#define FSL_CHASSIS3_SRDS2_REGSR 29
#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_CHASSIS3_EC1_REGSR 26
+#define FSL_CHASSIS3_EC2_REGSR 26
+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
#define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
#define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
@@ -597,7 +597,6 @@ int board_eth_init(bd_t *bis)
/* Register the real MDIO1 bus */
fm_memac_mdio_init(bis, memac_mdio0_info);
-
/* Register the muxing front-ends to the MDIO buses */
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);
ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);
@@ -37,6 +37,15 @@ void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
}
}
+void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)
+{
+ dpmac_info[dpmac_id].enabled = 1;
+ dpmac_info[dpmac_id].id = dpmac_id;
+ dpmac_info[dpmac_id].phy_addr = -1;
+ dpmac_info[dpmac_id].enet_if = enet_if;
+}
+
+
/*TODO what it do */
static int wriop_dpmac_to_index(int dpmac_id)
{
@@ -8,6 +8,7 @@
#include <fsl-mc/ldpaa_wriop.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
u32 dpmac_to_devdisr[] = {
[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,
@@ -85,3 +86,29 @@ void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
break;
}
}
+
+#ifdef CONFIG_SYS_FSL_HAS_RGMII
+void fsl_rgmii_init(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 ec;
+
+#ifdef CONFIG_SYS_FSL_EC1
+ ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
+ & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
+ ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
+
+ if (!ec)
+ wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);
+#endif
+
+#ifdef CONFIG_SYS_FSL_EC2
+ ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
+ & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
+ ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
+
+ if (!ec)
+ wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);
+#endif
+}
+#endif
@@ -69,4 +69,6 @@ void wriop_dpmac_disable(int);
void wriop_dpmac_enable(int);
phy_interface_t wriop_dpmac_enet_if(int, int);
void wriop_init_dpmac_qsgmii(int, int);
+void wriop_init_rgmii(void);
+void wriop_init_dpmac_enet_if(int , phy_interface_t);
#endif /* __LDPAA_WRIOP_H */