diff mbox

[U-Boot] armv8: fsl-layerscape: Put SATA code under SATA configs

Message ID 1503033876-23379-1-git-send-email-Ashish.Kumar@nxp.com
State Accepted
Commit bdbcb522568fe46dc6141ea1f799e2d08b0e3d76
Delegated to: York Sun
Headers show

Commit Message

Ashish Kumar Aug. 18, 2017, 5:24 a.m. UTC 
It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

York Sun Sept. 25, 2017, 5:29 p.m. UTC | #1 
On 08/17/2017 10:24 PM, Ashish Kumar wrote:
> It is not necessary for every SoC to have 2 SATA controller.
> So put SATA1, SATA2 code under respective defines.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
> ---

Applied to fsl-qoriq mater. Thanks.

York
diff mbox

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index ddb7d82..a704103 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -215,11 +215,14 @@  int sata_init(void)
 {
 	struct ccsr_ahci __iomem *ccsr_ahci;
 
+#ifdef CONFIG_SYS_SATA2
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
 	out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
+#endif
 
+#ifdef CONFIG_SYS_SATA1
 	ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
 	out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
 	out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
@@ -227,6 +230,7 @@  int sata_init(void)
 
 	ahci_init((void __iomem *)CONFIG_SYS_SATA1);
 	scsi_scan(false);
+#endif
 
 	return 0;
 }