sparc64: speed up etrap/rtrap on NG2 and later processors

For many sun4v processor types, reading or writing a privileged register
has a latency of 40 to 70 cycles.  Use a combination of the low-latency
allclean, otherw, normalw, and nop instructions in etrap and rtrap to
replace 2 rdpr and 5 wrpr instructions and improve etrap/rtrap
performance.  allclean, otherw, and normalw are available on NG2 and
later processors.

The average ticks to execute the flush windows trap ("ta 0x3") with and
without this patch on select platforms:

 CPU            Not patched     Patched    % Latency Reduction

 NG2            1762            1558            -11.58
 NG4            3619            3204            -11.47
 M7             3015            2624            -12.97
 SPARC64-X      829             770              -7.12

Signed-off-by: Anthony Yznaga <anthony.yznaga@oracle.com>
---
 arch/sparc/include/asm/trap_block.h |    2 ++
 arch/sparc/kernel/etrap_64.S        |   26 ++++++++++++++++++++++----
 arch/sparc/kernel/rtrap_64.S        |   13 +++++++++++--
 arch/sparc/kernel/setup_64.c        |   14 ++++++++++++++
 arch/sparc/kernel/vmlinux.lds.S     |    5 +++++
 5 files changed, 54 insertions(+), 6 deletions(-)

> On Aug 17, 2017, at 5:59 PM, Anthony Yznaga <anthony.yznaga@oracle.com> wrote:
> 
> --- a/arch/sparc/kernel/setup_64.c
> +++ b/arch/sparc/kernel/setup_64.c
> @@ -300,6 +300,20 @@ static void __init sun4v_patch(void)
> 		break;
> 	}
> 
> +	switch (sun4v_chip_type) {
> +	case SUN4V_CHIP_NIAGARA2:
> +	case SUN4V_CHIP_NIAGARA3:
> +	case SUN4V_CHIP_NIAGARA4:
> +	case SUN4V_CHIP_NIAGARA5:
> +	case SUN4V_CHIP_SPARC_M6:
> +	case SUN4V_CHIP_SPARC_M7:
> +	case SUN4V_CHIP_SPARC_M8:
> +	case SUN4V_CHIP_SPARC64X:
> +	case SUN4V_CHIP_SPARC_SN:
> +		sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
> +					&__fast_win_ctrl_1insn_patch_end);
> +	}

It was pointed out off-list that this is not future-proof.  The only
sun4v chip that does not support allclean, normalw, and otherw is
Niagara1, and any future sun4v-compliant chip must support the
instructions.  Rather than require a code change for new processors,
just skip hot patching for Niagara1.  I'll send out a v2 patch shortly.

Anthony--
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From: Anthony Yznaga <anthony.yznaga@oracle.com>
Date: Fri, 18 Aug 2017 12:25:31 -0700

> 
>> On Aug 17, 2017, at 5:59 PM, Anthony Yznaga <anthony.yznaga@oracle.com> wrote:
>> 
>> --- a/arch/sparc/kernel/setup_64.c
>> +++ b/arch/sparc/kernel/setup_64.c
>> @@ -300,6 +300,20 @@ static void __init sun4v_patch(void)
>> 		break;
>> 	}
>> 
>> +	switch (sun4v_chip_type) {
>> +	case SUN4V_CHIP_NIAGARA2:
>> +	case SUN4V_CHIP_NIAGARA3:
>> +	case SUN4V_CHIP_NIAGARA4:
>> +	case SUN4V_CHIP_NIAGARA5:
>> +	case SUN4V_CHIP_SPARC_M6:
>> +	case SUN4V_CHIP_SPARC_M7:
>> +	case SUN4V_CHIP_SPARC_M8:
>> +	case SUN4V_CHIP_SPARC64X:
>> +	case SUN4V_CHIP_SPARC_SN:
>> +		sun4v_patch_1insn_range(&__fast_win_ctrl_1insn_patch,
>> +					&__fast_win_ctrl_1insn_patch_end);
>> +	}
> 
> It was pointed out off-list that this is not future-proof.  The only
> sun4v chip that does not support allclean, normalw, and otherw is
> Niagara1, and any future sun4v-compliant chip must support the
> instructions.  Rather than require a code change for new processors,
> just skip hot patching for Niagara1.  I'll send out a v2 patch shortly.

I was going to say something about this as well.

You could test HWCAP_SPARC_BLKINIT or HWCAP_SPARC_N2.
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On Fri, Aug 18, 2017 at 3:15 PM, David Miller <davem@davemloft.net> wrote:
>> It was pointed out off-list that this is not future-proof.  The only
>> sun4v chip that does not support allclean, normalw, and otherw is
>> Niagara1, and any future sun4v-compliant chip must support the
>> instructions.  Rather than require a code change for new processors,
>> just skip hot patching for Niagara1.  I'll send out a v2 patch shortly.
>
> I was going to say something about this as well.
>
> You could test HWCAP_SPARC_BLKINIT or HWCAP_SPARC_N2.

Neither of those hwcaps are for these instructions.  hwcaps are
specific and are not intended to imply other features.  Please do not
use them that way.

-greg
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