From patchwork Sat Aug 12 06:29:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 800816 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="lyPxEmpo"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xTsbW30Dkz9t32 for ; Sat, 12 Aug 2017 16:36:39 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 0F10AC21D88; Sat, 12 Aug 2017 06:34:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 06517C21DCA; Sat, 12 Aug 2017 06:34:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id AD561C21DBE; Sat, 12 Aug 2017 06:33:50 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 7F085C21DC3 for ; Sat, 12 Aug 2017 06:33:46 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7C6Xjso032127; Sat, 12 Aug 2017 01:33:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502519625; bh=HlsrafPNST/pv4AvWDXW5snNxKsd327hRlu0YhFZOVI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lyPxEmpotmgG+QsHBIlwJHo0rPKg1688kOJwZ7UsWGjKcGC15lDAqorPKpYZL1APh iaeAK0zNnjHvkK7hBttmCmuVCMYfQugwn5MpOPVlAgzrNw4NKfpSPalz9S/kxSMnxW 2lr9tyZCkYlDlFgvrIuH66Ezx1uOV46V8QWQdMqA= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7C6XjR3015643; Sat, 12 Aug 2017 01:33:45 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Sat, 12 Aug 2017 01:33:44 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Sat, 12 Aug 2017 01:33:44 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Sat, 12 Aug 2017 01:33:44 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7C6XSkF020085; Sat, 12 Aug 2017 01:33:43 -0500 From: Lokesh Vutla To: Tom Rini , Date: Sat, 12 Aug 2017 11:59:28 +0530 Message-ID: <20170812062933.1325-8-lokeshvutla@ti.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170812062933.1325-1-lokeshvutla@ti.com> References: <20170812062933.1325-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH 07/12] board: ti: dra76-evm: Add DDR data X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" dra76-evm has the ddr parts connectedi running at 666MHz: EMIF1: MT41K512M16HA-125 AIT:A x 2 EMIF2: MT41K512M8RH-125-AAT:E x 4 Add support for configuring the above DDR parts. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/mach-omap2/omap5/hw_data.c | 1 + arch/arm/mach-omap2/omap5/sdram.c | 2 ++ board/ti/dra7xx/evm.c | 61 +++++++++++++++++++++++++++++++++++-- 3 files changed, 62 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index d6174fb5c7..d0d5d6804c 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -781,6 +781,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: + case DRA762_ES1_0: *regs = &ioregs_dra7xx_es1; break; case DRA722_ES1_0: diff --git a/arch/arm/mach-omap2/omap5/sdram.c b/arch/arm/mach-omap2/omap5/sdram.c index 7712923d85..67ff63b9f6 100644 --- a/arch/arm/mach-omap2/omap5/sdram.c +++ b/arch/arm/mach-omap2/omap5/sdram.c @@ -480,6 +480,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); break; + case DRA762_ES1_0: case DRA722_ES2_0: *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); @@ -709,6 +710,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) *iterations = sizeof(omap5_bug_00339_regs)/ sizeof(omap5_bug_00339_regs[0]); break; + case DRA762_ES1_0: case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 7ae8d2ff73..f9d0b05a16 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -210,6 +210,56 @@ const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { .emif_rd_wr_exec_thresh = 0x00000305 }; +const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra76 = { + .sdram_config_init = 0x61862B32, + .sdram_config = 0x61862B32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x0000514C, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD113783C, + .sdram_tim2 = 0x30B47FE3, + .sdram_tim3 = 0x409F8AD8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0824400D, + .emif_ddr_phy_ctlr_1 = 0x0E24400D, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, + .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, + .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, + .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif_2_regs_ddr3_666_mhz_1cs_dra76 = { + .sdram_config_init = 0x61862B32, + .sdram_config = 0x61862B32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x0000514C, + .ref_ctrl_final = 0x0000144A, + .sdram_tim1 = 0xD113781C, + .sdram_tim2 = 0x30B47FE3, + .sdram_tim3 = 0x409F8AD8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x5007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0824400D, + .emif_ddr_phy_ctlr_1 = 0x0E24400D, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, + .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, + .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, + .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) { u64 ram_size; @@ -235,6 +285,12 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) break; } break; + case DRA762_ES1_0: + if (emif_nr == 1) + *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra76; + else + *regs = &emif_2_regs_ddr3_666_mhz_1cs_dra76; + break; case DRA722_ES1_0: case DRA722_ES2_0: if (ram_size < CONFIG_MAX_MEM_MAPPED) @@ -290,6 +346,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) ram_size = board_ti_get_emif_size(); switch (omap_revision()) { + case DRA762_ES1_0: case DRA752_ES1_0: case DRA752_ES1_1: case DRA752_ES2_0: @@ -1010,8 +1067,8 @@ static inline void vtt_regulator_enable(void) if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) return; - /* Do not enable VTT for DRA722 */ - if (is_dra72x()) + /* Do not enable VTT for DRA722 or DRA76x */ + if (is_dra72x() || is_dra76x()) return; /*