From patchwork Sat Aug 12 06:29:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 800813 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Ha03wcci"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xTsZ11dZnz9t32 for ; Sat, 12 Aug 2017 16:35:21 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 012B0C21E02; Sat, 12 Aug 2017 06:33:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 152E3C21D92; Sat, 12 Aug 2017 06:33:38 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EF26FC21C73; Sat, 12 Aug 2017 06:33:34 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 058D6C21C26 for ; Sat, 12 Aug 2017 06:33:33 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7C6XWPv019328; Sat, 12 Aug 2017 01:33:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1502519612; bh=BCpKhSUBpCy0jH2Y7+LgAdojMWfxzqFLub3pR6/kzwE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ha03wcciavcAFyCOKTBQ6iaoojcGzPS9NU89ujhM6sFVJO1awsQvAlCv5Y+oGHRnF UyCWDPak5KSIHjt1yHahbS/53ufwCvrhmNQXYezW3oM7JGlmPjbGCo2c31bD1d09Fe 4FBVYzTGXeKmRy/QOAaWZX3LldfVGdLWRPli9lhQ= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7C6XWi0019654; Sat, 12 Aug 2017 01:33:32 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Sat, 12 Aug 2017 01:33:32 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Sat, 12 Aug 2017 01:33:32 -0500 Received: from a0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7C6XSk9020085; Sat, 12 Aug 2017 01:33:30 -0500 From: Lokesh Vutla To: Tom Rini , Date: Sat, 12 Aug 2017 11:59:22 +0530 Message-ID: <20170812062933.1325-2-lokeshvutla@ti.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170812062933.1325-1-lokeshvutla@ti.com> References: <20170812062933.1325-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH 01/12] arm: omap5+: Add board specific ldo powering X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" It is not necessary all omap5+ based uses the same PMIC to poweron mmc. So add support for enabling mmc based on board. Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/include/asm/omap_mmc.h | 1 + arch/arm/mach-omap2/omap5/hwinit.c | 16 ++++++---------- board/ti/dra7xx/evm.c | 14 ++++++++++++++ 3 files changed, 21 insertions(+), 10 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index f6eb51ee3c..fd33408622 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -174,4 +174,5 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio); void vmmc_pbias_config(uint voltage); +void board_mmc_poweron_ldo(uint voltage); #endif /* OMAP_MMC_H_ */ diff --git a/arch/arm/mach-omap2/omap5/hwinit.c b/arch/arm/mach-omap2/omap5/hwinit.c index afe59e0b58..42b0d6121c 100644 --- a/arch/arm/mach-omap2/omap5/hwinit.c +++ b/arch/arm/mach-omap2/omap5/hwinit.c @@ -455,10 +455,14 @@ void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, } #if defined(CONFIG_PALMAS_POWER) +__weak void board_mmc_poweron_ldo(uint voltage) +{ + palmas_mmc1_poweron_ldo(voltage); + +} void vmmc_pbias_config(uint voltage) { u32 value = 0; - struct vcores_data const *vcores = *omap_vcores; value = readl((*ctrl)->control_pbias); value &= ~SDCARD_PWRDNZ; @@ -467,15 +471,7 @@ void vmmc_pbias_config(uint voltage) value &= ~SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias); - if (vcores->core.pmic->i2c_slave_addr == 0x60) { - if (voltage == LDO_VOLT_3V0) - voltage = 0x19; - else if (voltage == LDO_VOLT_1V8) - voltage = 0xa; - lp873x_mmc1_poweron_ldo(voltage); - } else { - palmas_mmc1_poweron_ldo(voltage); - } + board_mmc_poweron_ldo(voltage); value = readl((*ctrl)->control_pbias); value |= SDCARD_BIAS_PWRDNZ; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 7d36f03fa1..e202ebf207 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -710,6 +710,20 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +void board_mmc_poweron_ldo(uint voltage) +{ + if (board_is_dra71x_evm()) { + if (voltage == LDO_VOLT_3V0) + voltage = 0x19; + else if (voltage == LDO_VOLT_1V8) + voltage = 0xa; + lp873x_mmc1_poweron_ldo(voltage); + } else { + palmas_mmc1_poweron_ldo(voltage); + } + +} #endif #ifdef CONFIG_USB_DWC3