@@ -5,6 +5,19 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#if defined(CONFIG_ROCKCHIP_RK3066) && defined(CONFIG_TPL_BUILD)
+ ldr r3, =0x10080900
+ ldr r0, [r3]
+ cmp r0, #1
+ movne r0, #1
+ strne r0, [r3]
+ beq out_of_bootrom
+ bx lr
+out_of_bootrom:
+ mov r0, #0
+ str r0, [r3]
+#endif
+
/*
* Execution starts on the instruction following this 4-byte header
* (containing the magic 'RK33').
@@ -26,6 +39,7 @@
*/
b reset /* may be overwritten --- should be 'nop' or a 'b reset' */
#endif
+
b reset
#if defined(CONFIG_ROCKCHIP_RK3399) && defined(CONFIG_SPL_BUILD)
@@ -47,6 +47,15 @@
_start:
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include <asm/arch/boot0.h>
+#endif
+
#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
.word CONFIG_SYS_DV_NOR_BOOT_CFG
#endif
@@ -60,15 +69,6 @@ _start:
ldr pc, _irq
ldr pc, _fiq
-#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
-/*
- * Various SoCs need something special and SoC-specific up front in
- * order to boot, allow them to set that in their boot0.h file and then
- * use it here.
- */
-#include <asm/arch/boot0.h>
-#endif
-
/*
*************************************************************************
*
@@ -13,6 +13,7 @@ CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
CONFIG_SYS_NS16550=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_BOOTDELAY=1
CONFIG_CONSOLE_MUX=y
CONFIG_DISPLAY_BOARDINFO=y