| Message ID | 20170811142735.2970-3-icenowy@aosc.io |
|---|---|
| State | New |
| Headers | show |
On Fri, Aug 11, 2017 at 10:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote: > The pin controller of H5 has three IRQs at the chip's GIC, which > represents three banks of pinctrl IRQs. However, the device tree used to > miss the third IRQ of the pin controller, which makes the PG bank IRQ > not usable. > > Add the missing IRQ to the pinctrl node. > > Fixes: 4e36de179f27 ("arm64: allwinner: h5: add Allwinner H5 .dtsi") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Applied as fixes for 4.13. ChenYu -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 732e2e06f503..d9a720bff05d 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -120,5 +120,8 @@ }; &pio { + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; compatible = "allwinner,sun50i-h5-pinctrl"; };
The pin controller of H5 has three IRQs at the chip's GIC, which represents three banks of pinctrl IRQs. However, the device tree used to miss the third IRQ of the pin controller, which makes the PG bank IRQ not usable. Add the missing IRQ to the pinctrl node. Fixes: 4e36de179f27 ("arm64: allwinner: h5: add Allwinner H5 .dtsi") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +++ 1 file changed, 3 insertions(+)