[U-Boot,v2,5/8] armv7: Add workaround for USB erratum A-009008

Submitted by Ran Wang on Aug. 11, 2017, 7:08 a.m.

Details

Message ID 1502435289-39000-5-git-send-email-ran.wang_1@nxp.com
State Superseded
Delegated to: York Sun
Headers show

Commit Message

Ran Wang Aug. 11, 2017, 7:08 a.m.
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is ovserved, change
set the same value.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
---
Change in v2:
	In function erratum_a009008():
	1.Put a blank line after variable declaration.

 arch/arm/cpu/armv7/ls102xa/Kconfig                |  6 ++++++
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 15 +++++++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 ++++
 3 files changed, 25 insertions(+)

Patch hide | download patch | download mbox

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 6a013b2..96e9782 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@  config ARCH_LS1021A
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010315
+	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -51,6 +52,11 @@  config SECURE_BOOT
 config SYS_FSL_ERRATUM_A010315
 	bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_ERRATUM_A009008
+	bool
+	help
+		Workaround for USB erratum A009008
+
 config SYS_FSL_SRDS_1
 	bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index b84a1a6..ac060bb 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,18 @@  unsigned int get_soc_major_rev(void)
 	return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+	u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+
+	val &= ~(0xF << 6);
+	out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
+
 void s_init(void)
 {
 }
@@ -146,6 +158,9 @@  int arch_soc_init(void)
 	 */
 	out_be32(&scfg->eddrtqcfg, 0x63b20042);
 
+	/* Erratum */
+	erratum_a009008();
+
 	return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..6ea8c4b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@  struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG1	0x00040000
 #define SCFG_CLUSTERPMCR_WFIL2EN	0x80000000
 
+#define SCFG_BASE			0x01570000
+#define SCFG_USB3PRM1CR			0x070
+#define USB_TXVREFTUNE			0x9
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
 	u32 dpslpcr;