From patchwork Thu Aug 10 13:12:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jackson Woodruff X-Patchwork-Id: 800199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-460175-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="YY5bHXK3"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xSpV01Bt0z9t2r for ; Thu, 10 Aug 2017 23:13:11 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:cc:message-id:date:mime-version:content-type; q= dns; s=default; b=bW/8znp7rDcF7ZNfQmZ4/EvcTyb52k/agPRiTpE+WouM1P BNdLl8EAb+pu39hKOkqyGwvx0Bj+vFV+Q8QMY7aDG4jxfsV44EncSOi9CPZpNr4x QQfrnVHyzf+QtL0tGcNuqtL0OKdPrtySTTFedt9frXX7L/3bw1a02iBwp62S8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:cc:message-id:date:mime-version:content-type; s= default; bh=wOwN0dy/crcYfKNRB66nFOJ34uk=; b=YY5bHXK3fZLaca4DxLbw naDhvRAoGtYy9y/JyFHao7EKMgRMxtllRQWrwu95Zr9TFufzqIk8pyqIYb0Kxc/U toYRDUiQQdPYg7xFS+q9QA8Zp4KJA00VxzI/JFSwaB1Mp6wHhbWKGmJIrX03F0gz 7b0K/zME7Jh/CmOVjDvxl68= Received: (qmail 31763 invoked by alias); 10 Aug 2017 13:13:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 31729 invoked by uid 89); 10 Aug 2017 13:12:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=jackson, Jackson X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 10 Aug 2017 13:12:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3E49D80D; Thu, 10 Aug 2017 06:12:53 -0700 (PDT) Received: from [10.2.206.195] (e112997-lin.cambridge.arm.com [10.2.206.195]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 94FAC3F577; Thu, 10 Aug 2017 06:12:52 -0700 (PDT) To: gcc-patches@gcc.gnu.org From: Jackson Woodruff Subject: [AArch64, PATCH] Improve Neon store of zero Cc: James Greenhalgh , richard.earnshaw@arm.com Message-ID: Date: Thu, 10 Aug 2017 14:12:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 X-IsSubscribed: yes Hi all, This patch changes patterns in aarch64-simd.md to replace movi v0.4s, 0 str q0, [x0, 16] With: stp xzr, xzr, [x0, 16] When we are storing zeros to vectors like this: void f(uint32x4_t *p) { uint32x4_t x = { 0, 0, 0, 0}; p[1] = x; } Bootstrapped and regtested on aarch64 with no regressions. OK for trunk? Jackson gcc/ 2017-08-09 Jackson Woodruff * aarch64-simd.md (mov): No longer force zero immediate into register. (*aarch64_simd_mov): Add new case for stp using zero immediate. gcc/testsuite 2017-08-09 Jackson Woodruff * gcc.target/aarch64/simd/neon_str_zero.c: New. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 74de9b8c89dd5e4e3d87504594c969de0e0128ce..0149a742d34ae4fd5b3fd705b03c845f94aa1d59 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -23,7 +23,10 @@ (match_operand:VALL_F16 1 "general_operand" ""))] "TARGET_SIMD" " - if (GET_CODE (operands[0]) == MEM) + if (GET_CODE (operands[0]) == MEM + && !(aarch64_simd_imm_zero (operands[1], mode) + && aarch64_legitimate_address_p (mode, operands[0], + PARALLEL, 1))) operands[1] = force_reg (mode, operands[1]); " ) @@ -94,63 +97,70 @@ (define_insn "*aarch64_simd_mov" [(set (match_operand:VD 0 "nonimmediate_operand" - "=w, m, w, ?r, ?w, ?r, w") + "=w, m, m, w, ?r, ?w, ?r, w") (match_operand:VD 1 "general_operand" - "m, w, w, w, r, r, Dn"))] + "m, Dz, w, w, w, r, r, Dn"))] "TARGET_SIMD - && (register_operand (operands[0], mode) - || register_operand (operands[1], mode))" + && ((register_operand (operands[0], mode) + || register_operand (operands[1], mode)) + || (memory_operand (operands[0], mode) + && immediate_operand (operands[1], mode)))" { switch (which_alternative) { case 0: return "ldr\\t%d0, %1"; - case 1: return "str\\t%d1, %0"; - case 2: return "mov\t%0., %1."; - case 3: return "umov\t%0, %1.d[0]"; - case 4: return "fmov\t%d0, %1"; - case 5: return "mov\t%0, %1"; - case 6: + case 1: return "str\\txzr, %0"; + case 2: return "str\\t%d1, %0"; + case 3: return "mov\t%0., %1."; + case 4: return "umov\t%0, %1.d[0]"; + case 5: return "fmov\t%d0, %1"; + case 6: return "mov\t%0, %1"; + case 7: return aarch64_output_simd_mov_immediate (operands[1], mode, 64); default: gcc_unreachable (); } } - [(set_attr "type" "neon_load1_1reg, neon_store1_1reg,\ + [(set_attr "type" "neon_load1_1reg, neon_stp, neon_store1_1reg,\ neon_logic, neon_to_gp, f_mcr,\ mov_reg, neon_move")] ) (define_insn "*aarch64_simd_mov" [(set (match_operand:VQ 0 "nonimmediate_operand" - "=w, m, w, ?r, ?w, ?r, w") + "=w, Ump, m, w, ?r, ?w, ?r, w") (match_operand:VQ 1 "general_operand" - "m, w, w, w, r, r, Dn"))] + "m, Dz, w, w, w, r, r, Dn"))] "TARGET_SIMD - && (register_operand (operands[0], mode) - || register_operand (operands[1], mode))" + && ((register_operand (operands[0], mode) + || register_operand (operands[1], mode)) + || (memory_operand (operands[0], mode) + && immediate_operand (operands[1], mode)))" { switch (which_alternative) { case 0: return "ldr\\t%q0, %1"; case 1: - return "str\\t%q1, %0"; + return "stp\\txzr, xzr, %0"; case 2: - return "mov\t%0., %1."; + return "str\\t%q1, %0"; case 3: + return "mov\t%0., %1."; case 4: case 5: - return "#"; case 6: + return "#"; + case 7: return aarch64_output_simd_mov_immediate (operands[1], mode, 128); default: gcc_unreachable (); } } [(set_attr "type" "neon_load1_1reg, neon_store1_1reg,\ - neon_logic, multiple, multiple, multiple,\ - neon_move") - (set_attr "length" "4,4,4,8,8,8,4")] + neon_stp, neon_logic, multiple, multiple,\ + multiple, neon_move") + (set_attr "length" "4,4,4,4,8,8,8,4")] ) ;; When storing lane zero we can use the normal STR and its more permissive diff --git a/gcc/testsuite/gcc.target/aarch64/simd/neon_str_zero.c b/gcc/testsuite/gcc.target/aarch64/simd/neon_str_zero.c new file mode 100644 index 0000000000000000000000000000000000000000..07198de109432b530745cc540790303ae0245efb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/simd/neon_str_zero.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +#include + +void +f (uint32x4_t *p) +{ + uint32x4_t x = { 0, 0, 0, 0}; + p[1] = x; + + /* { dg-final { scan-assembler "stp\txzr, xzr," } } */ +} + +void +g (float32x2_t *p) +{ + float32x2_t x = {0.0, 0.0}; + p[0] = x; + + /* { dg-final { scan-assembler "str\txzr, " } } */ +}