[4/4] phb4: Enhanced PCIe training tracing

Submitted by Michael Neuling on Aug. 10, 2017, 6:02 a.m.

Details

Message ID 20170810060253.11928-4-mikey@neuling.org
State Accepted
Headers show

Commit Message

Michael Neuling Aug. 10, 2017, 6:02 a.m.
This add more details to the PCI training tracing (aka Rick Mata
mode). It enables the PCIe Link Training and Status State
Machine (LTSSM) tracing and details on speed and link width.

Output now looks like this when enabled (via nvram):

[    1.096995141,3] PHB#0000[0:0]: TRACE:0x0000001101000000  0ms          GEN1:x16:detect
[    1.102849137,3] PHB#0000[0:0]: TRACE:0x0000102101000000 11ms presence GEN1:x16:polling
[    1.104341838,3] PHB#0000[0:0]: TRACE:0x0000182101000000 14ms training GEN1:x16:polling
[    1.104357444,3] PHB#0000[0:0]: TRACE:0x00001c5101000000 14ms training GEN1:x16:recovery
[    1.104580394,3] PHB#0000[0:0]: TRACE:0x00001c5103000000 14ms training GEN3:x16:recovery
[    1.123259359,3] PHB#0000[0:0]: TRACE:0x00001c5104000000 51ms training GEN4:x16:recovery
[    1.141737656,3] PHB#0000[0:0]: TRACE:0x0000144104000000 87ms presence GEN4:x16:L0
[    1.141752318,3] PHB#0000[0:0]: TRACE:0x0000154904000000 87ms trained  GEN4:x16:L0
[    1.141757964,3] PHB#0000[0:0]: TRACE: Link trained.
[    1.096834019,3] PHB#0001[0:1]: TRACE:0x0000001101000000  0ms          GEN1:x16:detect
[    1.105578525,3] PHB#0001[0:1]: TRACE:0x0000102101000000 17ms presence GEN1:x16:polling
[    1.112763075,3] PHB#0001[0:1]: TRACE:0x0000183101000000 31ms training GEN1:x16:config
[    1.112778956,3] PHB#0001[0:1]: TRACE:0x00001c5081000000 31ms training GEN1:x08:recovery
[    1.113002083,3] PHB#0001[0:1]: TRACE:0x00001c5083000000 31ms training GEN3:x08:recovery
[    1.114833873,3] PHB#0001[0:1]: TRACE:0x0000144083000000 35ms presence GEN3:x08:L0
[    1.114848832,3] PHB#0001[0:1]: TRACE:0x0000154883000000 35ms trained  GEN3:x08:L0
[    1.114854650,3] PHB#0001[0:1]: TRACE: Link trained.

Signed-off-by: Michael Neuling <mikey@neuling.org>
---
 hw/phb4.c           | 48 ++++++++++++++++++++++++++++++++++++++++++++++--
 include/phb4-regs.h | 17 +++++++++++++++++
 2 files changed, 63 insertions(+), 2 deletions(-)

Patch hide | download patch | download mbox

diff --git a/hw/phb4.c b/hw/phb4.c
index b207b6a1cf..6cddda2da8 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -2262,16 +2262,53 @@  static void phb4_train_info(struct phb4 *p, uint64_t reg, unsigned long time)
 {
 	char s[80];
 
-	snprintf(s, sizeof(s), "TRACE: 0x%016llx % 2lims",
+	snprintf(s, sizeof(s), "TRACE:0x%016llx % 2lims",
 		 reg, tb_to_msecs(time));
 
 	if (reg & PHB_PCIE_DLP_TL_LINKACT)
-		snprintf(s, sizeof(s), "%s trained", s);
+		snprintf(s, sizeof(s), "%s trained ", s);
 	else if (reg & PHB_PCIE_DLP_TRAINING)
 		snprintf(s, sizeof(s), "%s training", s);
 	else if (reg & PHB_PCIE_DLP_INBAND_PRESENCE)
 		snprintf(s, sizeof(s), "%s presence", s);
+	else
+		snprintf(s, sizeof(s), "%s         ", s);
+
+	snprintf(s, sizeof(s), "%s GEN%lli:x%02lli:", s,
+		 GETFIELD(PHB_PCIE_DLP_LINK_SPEED, reg),
+		 GETFIELD(PHB_PCIE_DLP_LINK_WIDTH, reg));
 
+	switch (GETFIELD(PHB_PCIE_DLP_LTSSM_TRC, reg)) {
+	case PHB_PCIE_DLP_LTSSM_RESET:
+		snprintf(s, sizeof(s), "%sreset", s);
+		break;
+	case PHB_PCIE_DLP_LTSSM_DETECT:
+		snprintf(s, sizeof(s), "%sdetect", s);
+		break;
+	case PHB_PCIE_DLP_LTSSM_POLLING:
+		snprintf(s, sizeof(s), "%spolling", s);
+		break;
+	case PHB_PCIE_DLP_LTSSM_CONFIG:
+		snprintf(s, sizeof(s), "%sconfig", s);
+		break;
+	case PHB_PCIE_DLP_LTSSM_L0:
+		snprintf(s, sizeof(s), "%sL0", s);
+		break;
+	case PHB_PCIE_DLP_LTSSM_REC:
+		snprintf(s, sizeof(s), "%srecovery", s);
+		break;
+	case PHB_PCIE_DLP_LTSSM_L1:
+		snprintf(s, sizeof(s), "%sL1", s);
+		break;
+	case PHB_PCIE_DLP_LTSSM_L2:
+		snprintf(s, sizeof(s), "%sL2", s);
+		break;
+	case PHB_PCIE_DLP_LTSSM_HOTRESET:
+		snprintf(s, sizeof(s), "%shotreset", s);
+		break;
+	default:
+		snprintf(s, sizeof(s), "%sunvalid", s);
+	}
 	PHBERR(p, "%s\n", s);
 }
 
@@ -2565,6 +2602,13 @@  static int64_t phb4_freset(struct pci_slot *slot)
 		/* Clear link errors before we deassert PERST */
 		phb4_err_clear_regb(p);
 
+		if (pci_tracing) {
+			/* Enable tracing */
+			reg = in_be64(p->regs + PHB_PCIE_DLP_TRWCTL);
+			out_be64(p->regs + PHB_PCIE_DLP_TRWCTL,
+				 reg | PHB_PCIE_DLP_TRWCTL_EN);
+		}
+
 		PHBDBG(p, "FRESET: Deassert\n");
 		reg = in_be64(p->regs + PHB_PCIE_CRESET);
 		reg |= PHB_PCIE_CRESET_PERST_N;
diff --git a/include/phb4-regs.h b/include/phb4-regs.h
index f06a1540ac..59c308ecd8 100644
--- a/include/phb4-regs.h
+++ b/include/phb4-regs.h
@@ -282,11 +282,28 @@ 
 #define	  PHB_PCIE_HPSTAT_PRESENCE	PPC_BIT(10)
 
 #define PHB_PCIE_DLP_TRAIN_CTL		0x1A40
+#define	  PHB_PCIE_DLP_LINK_WIDTH	PPC_BITMASK(30,35)
+#define	  PHB_PCIE_DLP_LINK_SPEED	PPC_BITMASK(36,39)
+#define	  PHB_PCIE_DLP_LTSSM_TRC	PPC_BITMASK(24,27)
+#define	    PHB_PCIE_DLP_LTSSM_RESET	0
+#define	    PHB_PCIE_DLP_LTSSM_DETECT	1
+#define	    PHB_PCIE_DLP_LTSSM_POLLING	2
+#define	    PHB_PCIE_DLP_LTSSM_CONFIG	3
+#define	    PHB_PCIE_DLP_LTSSM_L0      	4
+#define	    PHB_PCIE_DLP_LTSSM_REC     	5
+#define	    PHB_PCIE_DLP_LTSSM_L1      	6
+#define	    PHB_PCIE_DLP_LTSSM_L2      	7
+#define	    PHB_PCIE_DLP_LTSSM_HOTRESET	8
+#define	    PHB_PCIE_DLP_LTSSM_DISABLED	9
+#define	    PHB_PCIE_DLP_LTSSM_LOOPBACK	10
 #define	  PHB_PCIE_DLP_TL_LINKACT	PPC_BIT(23)
 #define   PHB_PCIE_DLP_DL_PGRESET	PPC_BIT(22)
 #define   PHB_PCIE_DLP_TRAINING		PPC_BIT(20)
 #define   PHB_PCIE_DLP_INBAND_PRESENCE  PPC_BIT(19)
 
+#define PHB_PCIE_DLP_TRWCTL		0x1A80
+#define   PHB_PCIE_DLP_TRWCTL_EN	PPC_BIT(0)
+
 #define PHB_PCIE_DLP_ERRLOG1		0x1AA0
 #define PHB_PCIE_DLP_ERRLOG2		0x1AA8
 #define PHB_PCIE_DLP_ERR_STATUS		0x1AB0