From patchwork Wed Aug 9 20:12:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 799918 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xSMt16ksSz9s0Z for ; Thu, 10 Aug 2017 06:14:01 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A7949C21DF3; Wed, 9 Aug 2017 20:13:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 714D4C21DCE; Wed, 9 Aug 2017 20:13:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EE726C21DBE; Wed, 9 Aug 2017 20:13:27 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lists.denx.de (Postfix) with ESMTPS id 70F99C21D58 for ; Wed, 9 Aug 2017 20:13:23 +0000 (UTC) Received: from localhost.localdomain.ziswiler.net ([89.217.76.191]) by mrelay.perfora.net (mreueus001 [74.208.5.2]) with ESMTPA (Nemesis) id 0MWRTQ-1e7UbA04l8-00XeGJ; Wed, 09 Aug 2017 22:13:14 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Wed, 9 Aug 2017 22:12:42 +0200 Message-Id: <20170809201242.16355-7-marcel@ziswiler.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170809201242.16355-1-marcel@ziswiler.com> References: <20170809201242.16355-1-marcel@ziswiler.com> X-Provags-ID: V03:K0:k2eId/w6mRGWXZnCPHeu1mGBawhIGQP/H2JCaahL96+IOVo3ssk yjYpAz9obCgmDPplxkQMGPmvQZkfVWCcEfjO/t0yGvq9MzgWpio1OoRkmf+7L0pkcTovvHM AUfM01jXlFyPZJ9lXC2dOdhUwASjeiTFfBYMDltTB6E/VDGMWaH3vtSpBKZHI05j1+soQAi 2e+r2tryzr5zniBnKyt/A== X-UI-Out-Filterresults: notjunk:1; V01:K0:XhQ7e9uoaD0=:fKdWhTXXkDYaE4JO4E0TQM b0zGBfhHo13yCwtfl77+EwoYSlGA280PUdeyqj9gb25UlX+ceHisRIRmbqORQMF3SJAbgrcrs ugDsfM0ypoZoUVeGNGfyScGmPN7x3t/QcVfu8ENHakRonyYTnLExMoEzW4xW+hMcX4JE+bV3N WpJSB/7XV62XKUXSbDURYKh3l538Y7L1yGC7Lnqhn594x0E14DEiQor+xUfQ5pIJUCJdzCwwF 2LJMhxhSKgEAG2AsiEXiYNfX1NtFXhH5pYkThX6//rCO5gggrAgawNWEEmQQl//GWZoZM8Hpz sitXxVJDOPiBfsT8vW8xZ0YLCLIs3beeNkwzFicOLAyiIxXAYfKNXw69IUBTASv+yrZgmlTsQ YcEKjzRLIt3uJ2yvdpOMwzw4r6/wMK7IDxxv4sOvxd2VqnCyfrtY8kTnCEVdu2F7HaRsEx+JS gHGuYg/ZWkfMrh44JhDe6ItPjOukzVO2Z718XEzMc28l95DsJSWLJPbtqG98I05BepmLiJPva KeM173ZD1ZNjjdIFuECBsKOF1JtmWenUiAtrTXLoz6SwzTtVZ/nB8KaBA+h6KnTwiVIUh0yC9 ulfTmfVit/jn0P1j++Fq30eR+wsA4xdBmvaV303NF+TfyFgFfjF1XbuOw+NUE5hn5nlssWV6C s2EZlJn/bgaX8TDtm21V2YeYuA5GtSM74HkEPcBuZsK/KQwXGZmlUxsmKYLktWhkNLqHf7e2k jCoFSYVy2hh6i31p1WnuQPRGXJzWBISjxuRFQQ== Cc: Marcel Ziswiler Subject: [U-Boot] [PATCH v4 6/6] apalis-tk1: fix pcie reset for reliable gigabit ethernet operation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler It turns out that the current PCIe reset implementation in the PCIe board init function is not quite working reliably due to PCIe reset timing violations. Fix this by overriding the tegra_pcie_board_port_reset() function. Also allow optionally bringing up the PCIe switch as found on the Apalis Evaluation board. Note however that the Apalis PCIe port is also left disabled in the device tree by default. Signed-off-by: Marcel Ziswiler --- Changes in v4: None Changes in v3: - Stick to struct tegra_pcie_port as suggested by Stephen. - Introduce proper CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT Kconfig option as suggested by Stephen. Changes in v2: None board/toradex/apalis-tk1/Kconfig | 8 ++ board/toradex/apalis-tk1/apalis-tk1.c | 249 +++++++++++++++++++++------------- 2 files changed, 163 insertions(+), 94 deletions(-) diff --git a/board/toradex/apalis-tk1/Kconfig b/board/toradex/apalis-tk1/Kconfig index 05407ad..159b8fb 100644 --- a/board/toradex/apalis-tk1/Kconfig +++ b/board/toradex/apalis-tk1/Kconfig @@ -25,6 +25,14 @@ config TDX_CFG_BLOCK_PART config TDX_CFG_BLOCK_OFFSET default "-512" +config APALIS_TK1_PCIE_EVALBOARD_INIT + bool "Apalis Evaluation Board PCIe Initialisation" + help + Bring up the Apalis PCIe port with the PCIe switch as found on the + Apalis Evaluation board. Note that by default the PCIe port is also + left disabled in the device tree which needs changing as well for this + to actually work. + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index 5de61e7..ca2d61d 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -5,17 +5,26 @@ */ #include +#include #include #include #include #include #include +#include #include +#include #include "../common/tdx-common.h" #include "pinmux-config-apalis-tk1.h" -#define LAN_RESET_N TEGRA_GPIO(S, 2) +#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6) +#define LAN_RESET_N TEGRA_GPIO(S, 2) +#define LAN_WAKE_N TEGRA_GPIO(O, 5) +#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT +#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */ +#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4) +#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */ int arch_misc_init(void) { @@ -59,123 +68,175 @@ void pinmux_init(void) } #ifdef CONFIG_PCI_TEGRA -int tegra_pcie_board_init(void) +/* TODO: Convert to driver model */ +static int as3722_sd_enable(struct udevice *pmic, unsigned int sd) { - /* TODO: Convert to driver model - struct udevice *pmic; int err; - err = as3722_init(&pmic); + if (sd > 6) + return -EINVAL; + + err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd); if (err) { - error("failed to initialize AS3722 PMIC: %d\n", err); + error("failed to update SD control register: %d", err); return err; } - err = as3722_sd_enable(pmic, 4); - if (err < 0) { - error("failed to enable SD4: %d\n", err); - return err; - } + return 0; +} - err = as3722_sd_set_voltage(pmic, 4, 0x24); - if (err < 0) { - error("failed to set SD4 voltage: %d\n", err); - return err; - } +/* TODO: Convert to driver model */ +static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo) +{ + int err; + u8 ctrl_reg = AS3722_LDO_CONTROL0; - err = as3722_gpio_configure(pmic, 1, AS3722_GPIO_OUTPUT_VDDH | - AS3722_GPIO_INVERT); - if (err < 0) { - error("failed to configure GPIO#1 as output: %d\n", err); - return err; - } + if (ldo > 11) + return -EINVAL; - err = as3722_gpio_direction_output(pmic, 2, 1); - if (err < 0) { - error("failed to set GPIO#2 high: %d\n", err); - return err; + if (ldo > 7) { + ctrl_reg = AS3722_LDO_CONTROL1; + ldo -= 8; } - */ - /* Reset I210 Gigabit Ethernet Controller */ - gpio_request(LAN_RESET_N, "LAN_RESET_N"); - gpio_direction_output(LAN_RESET_N, 0); - - /* - * Make sure we don't get any back feeding from LAN_WAKE_N resp. - * DEV_OFF_N - */ - gpio_request(TEGRA_GPIO(O, 5), "LAN_WAKE_N"); - gpio_direction_output(TEGRA_GPIO(O, 5), 0); - - gpio_request(TEGRA_GPIO(O, 6), "LAN_DEV_OFF_N"); - gpio_direction_output(TEGRA_GPIO(O, 6), 0); - - /* Make sure LDO9 and LDO10 are initially enabled @ 0V */ - /* TODO: Convert to driver model - err = as3722_ldo_enable(pmic, 9); - if (err < 0) { - error("failed to enable LDO9: %d\n", err); - return err; - } - err = as3722_ldo_enable(pmic, 10); - if (err < 0) { - error("failed to enable LDO10: %d\n", err); - return err; - } - err = as3722_ldo_set_voltage(pmic, 9, 0x80); - if (err < 0) { - error("failed to set LDO9 voltage: %d\n", err); - return err; - } - err = as3722_ldo_set_voltage(pmic, 10, 0x80); - if (err < 0) { - error("failed to set LDO10 voltage: %d\n", err); + err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo); + if (err) { + error("failed to update LDO control register: %d", err); return err; } - */ - mdelay(100); - - /* Make sure controller gets enabled by disabling DEV_OFF_N */ - gpio_set_value(TEGRA_GPIO(O, 6), 1); + return 0; +} - /* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototypes */ - /* TODO: Convert to driver model - err = as3722_ldo_set_voltage(pmic, 9, 0xff); - if (err < 0) { - error("failed to set LDO9 voltage: %d\n", err); - return err; +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(pmic_as3722), &dev); + if (ret) { + debug("%s: Failed to find PMIC\n", __func__); + return ret; } - err = as3722_ldo_set_voltage(pmic, 10, 0xff); - if (err < 0) { - error("failed to set LDO10 voltage: %d\n", err); - return err; + + ret = as3722_sd_enable(dev, 4); + if (ret < 0) { + error("failed to enable SD4: %d\n", ret); + return ret; } - */ - mdelay(100); - gpio_set_value(LAN_RESET_N, 1); + ret = as3722_sd_set_voltage(dev, 4, 0x24); + if (ret < 0) { + error("failed to set SD4 voltage: %d\n", ret); + return ret; + } -#ifdef APALIS_TK1_PCIE_EVALBOARD_INIT -#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */ -#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4) + gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N"); + gpio_request(LAN_RESET_N, "LAN_RESET_N"); + gpio_request(LAN_WAKE_N, "LAN_WAKE_N"); - /* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation - Board */ +#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT gpio_request(PEX_PERST_N, "PEX_PERST_N"); gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL"); - gpio_direction_output(PEX_PERST_N, 0); - gpio_direction_output(RESET_MOCI_CTRL, 0); - /* Must be asserted for 100 ms after power and clocks are stable */ - mdelay(100); - gpio_set_value(PEX_PERST_N, 1); - /* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until - 900 us After PEX_PERST# De-assertion */ - mdelay(1); - gpio_set_value(RESET_MOCI_CTRL, 1); -#endif /* APALIS_T30_PCIE_EVALBOARD_INIT */ +#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */ return 0; } + +void tegra_pcie_board_port_reset(struct tegra_pcie_port *port) +{ + int index = tegra_pcie_port_index_of_port(port); + if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_PMIC, + DM_GET_DRIVER(pmic_as3722), + &dev); + if (ret) { + debug("%s: Failed to find PMIC\n", __func__); + return; + } + + /* Reset I210 Gigabit Ethernet Controller */ + gpio_direction_output(LAN_RESET_N, 0); + + /* + * Make sure we don't get any back feeding from DEV_OFF_N resp. + * LAN_WAKE_N + */ + gpio_direction_output(LAN_DEV_OFF_N, 0); + gpio_direction_output(LAN_WAKE_N, 0); + + /* Make sure LDO9 and LDO10 are initially enabled @ 0V */ + ret = as3722_ldo_enable(dev, 9); + if (ret < 0) { + error("failed to enable LDO9: %d\n", ret); + return; + } + ret = as3722_ldo_enable(dev, 10); + if (ret < 0) { + error("failed to enable LDO10: %d\n", ret); + return; + } + ret = as3722_ldo_set_voltage(dev, 9, 0x80); + if (ret < 0) { + error("failed to set LDO9 voltage: %d\n", ret); + return; + } + ret = as3722_ldo_set_voltage(dev, 10, 0x80); + if (ret < 0) { + error("failed to set LDO10 voltage: %d\n", ret); + return; + } + + /* Make sure controller gets enabled by disabling DEV_OFF_N */ + gpio_set_value(LAN_DEV_OFF_N, 1); + + /* + * Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype + * V1.0A and sample V1.0B and newer modules + */ + ret = as3722_ldo_set_voltage(dev, 9, 0xff); + if (ret < 0) { + error("failed to set LDO9 voltage: %d\n", ret); + return; + } + ret = as3722_ldo_set_voltage(dev, 10, 0xff); + if (ret < 0) { + error("failed to set LDO10 voltage: %d\n", ret); + return; + } + + /* + * Must be asserted for 100 ms after power and clocks are stable + */ + mdelay(100); + + gpio_set_value(LAN_RESET_N, 1); + } else if (index == 0) { /* Apalis PCIe */ +#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT + /* + * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis + * Evaluation Board + */ + gpio_direction_output(PEX_PERST_N, 0); + gpio_direction_output(RESET_MOCI_CTRL, 0); + + /* + * Must be asserted for 100 ms after power and clocks are stable + */ + mdelay(100); + + gpio_set_value(PEX_PERST_N, 1); + /* + * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed + * Until 900 us After PEX_PERST# De-assertion + */ + mdelay(1); + gpio_set_value(RESET_MOCI_CTRL, 1); +#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */ + } +} #endif /* CONFIG_PCI_TEGRA */