[5/8] pinctrl: sh-pfc: r8a77995: Add EthernetAVB pins, groups and functions

Submitted by Yoshihiro Shimoda on Aug. 9, 2017, 12:19 p.m.

Details

Message ID 1502281187-24068-6-git-send-email-yoshihiro.shimoda.uh@renesas.com
State New
Headers show

Commit Message

Yoshihiro Shimoda Aug. 9, 2017, 12:19 p.m.
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 178 ++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

Comments

Geert Uytterhoeven Aug. 16, 2017, 11:06 a.m.
Hi Shimoda-san, Kihara-san,

On Wed, Aug 9, 2017 at 2:19 PM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

But before I apply this, please see my question below...

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c

> +static const char * const avb0_groups[] = {
> +       "avb0_td",
> +       "avb0_rd",
> +       "avb0_tx_ctl",
> +       "avb0_rx_ctl",
> +       "avb0_txc",
> +       "avb0_rxc",
> +       "avb0_txcrefclk",
> +       "avb0_link",
> +       "avb0_magic",
> +       "avb0_phy_int",
> +       "avb0_mdc",
> +       "avb0_mdio",
> +       "avb0_avtp_pps_a",
> +       "avb0_avtp_match_a",
> +       "avb0_avtp_capture_a",
> +       "avb0_avtp_pps_b",
> +       "avb0_avtp_match_b",
> +       "avb0_avtp_capture_b",
> +};

Is there any specific reason this uses a different split than the
EtherAVB groups
in pinctrl drivers for other SoCs?

Note that I do understand that the different prefix ("avb0" vs. "avb")
was used to
match the R-Car D3 datasheet, which is thus OK.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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Patch hide | download patch | download mbox

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 96c97ff..9eb0cef 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -936,6 +936,144 @@  enum {
 	PINMUX_GPIO_GP_ALL(),
 };
 
+/* - EtherAVB --------------------------------------------------------------- */
+static const unsigned int avb0_td_pins[] = {
+	/*
+	 * AVB0_TD0, AVB0_TD1,
+	 * AVB0_TD2, AVB0_TD3,
+	 */
+	RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
+	RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
+};
+static const unsigned int avb0_td_mux[] = {
+	AVB0_TD0_MARK, AVB0_TD1_MARK,
+	AVB0_TD2_MARK, AVB0_TD3_MARK,
+};
+static const unsigned int avb0_rd_pins[] = {
+	/*
+	 * AVB0_RD0, AVB0_RD1,
+	 * AVB0_RD2, AVB0_RD3,
+	 */
+	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
+};
+static const unsigned int avb0_rd_mux[] = {
+	AVB0_RD0_MARK, AVB0_RD1_MARK,
+	AVB0_RD2_MARK, AVB0_RD3_MARK,
+};
+static const unsigned int avb0_tx_ctl_pins[] = {
+	/* AVB0_TX_CTL */
+	RCAR_GP_PIN(5, 9),
+};
+static const unsigned int avb0_tx_ctl_mux[] = {
+	AVB0_TX_CTL_MARK,
+};
+static const unsigned int avb0_rx_ctl_pins[] = {
+	/* AVB0_RX_CTL */
+	RCAR_GP_PIN(5, 3),
+};
+static const unsigned int avb0_rx_ctl_mux[] = {
+	AVB0_RX_CTL_MARK,
+};
+static const unsigned int avb0_txc_pins[] = {
+	/* AVB0_TXC */
+	RCAR_GP_PIN(5, 10),
+};
+static const unsigned int avb0_txc_mux[] = {
+	AVB0_TXC_MARK,
+};
+static const unsigned int avb0_rxc_pins[] = {
+	/* AVB0_RXC */
+	RCAR_GP_PIN(5, 4),
+};
+static const unsigned int avb0_rxc_mux[] = {
+	AVB0_RXC_MARK,
+};
+static const unsigned int avb0_txcrefclk_pins[] = {
+	/* AVB0_TXCREFCLK */
+	RCAR_GP_PIN(5, 15),
+};
+static const unsigned int avb0_txcrefclk_mux[] = {
+	AVB0_TXCREFCLK_MARK,
+};
+static const unsigned int avb0_link_pins[] = {
+	/* AVB0_LINK */
+	RCAR_GP_PIN(5, 20),
+};
+static const unsigned int avb0_link_mux[] = {
+	AVB0_LINK_MARK,
+};
+static const unsigned int avb0_magic_pins[] = {
+	/* AVB0_MAGIC */
+	RCAR_GP_PIN(5, 18),
+};
+static const unsigned int avb0_magic_mux[] = {
+	AVB0_MAGIC_MARK,
+};
+static const unsigned int avb0_phy_int_pins[] = {
+	/* AVB0_PHY_INT */
+	RCAR_GP_PIN(5, 19),
+};
+static const unsigned int avb0_phy_int_mux[] = {
+	AVB0_PHY_INT_MARK,
+};
+static const unsigned int avb0_mdc_pins[] = {
+	/* AVB0_MDC */
+	RCAR_GP_PIN(5, 17),
+};
+static const unsigned int avb0_mdc_mux[] = {
+	AVB0_MDC_MARK,
+};
+static const unsigned int avb0_mdio_pins[] = {
+	/* AVB0_MDIO */
+	RCAR_GP_PIN(5, 16),
+};
+static const unsigned int avb0_mdio_mux[] = {
+	AVB0_MDIO_MARK,
+};
+static const unsigned int avb0_avtp_pps_a_pins[] = {
+	/* AVB0_AVTP_PPS_A */
+	RCAR_GP_PIN(5, 2),
+};
+static const unsigned int avb0_avtp_pps_a_mux[] = {
+	AVB0_AVTP_PPS_A_MARK,
+};
+static const unsigned int avb0_avtp_match_a_pins[] = {
+	/* AVB0_AVTP_MATCH_A */
+	RCAR_GP_PIN(5, 1),
+};
+static const unsigned int avb0_avtp_match_a_mux[] = {
+	AVB0_AVTP_MATCH_A_MARK,
+};
+static const unsigned int avb0_avtp_capture_a_pins[] = {
+	/* AVB0_AVTP_CAPTURE_A */
+	RCAR_GP_PIN(5, 0),
+};
+static const unsigned int avb0_avtp_capture_a_mux[] = {
+	AVB0_AVTP_CAPTURE_A_MARK,
+};
+static const unsigned int avb0_avtp_pps_b_pins[] = {
+	/* AVB0_AVTP_PPS_B */
+	RCAR_GP_PIN(4, 16),
+};
+static const unsigned int avb0_avtp_pps_b_mux[] = {
+	AVB0_AVTP_PPS_B_MARK,
+};
+static const unsigned int avb0_avtp_match_b_pins[] = {
+	/*  AVB0_AVTP_MATCH_B */
+	RCAR_GP_PIN(4, 18),
+};
+static const unsigned int avb0_avtp_match_b_mux[] = {
+	AVB0_AVTP_MATCH_B_MARK,
+};
+static const unsigned int avb0_avtp_capture_b_pins[] = {
+	/* AVB0_AVTP_CAPTURE_B */
+	RCAR_GP_PIN(4, 17),
+};
+static const unsigned int avb0_avtp_capture_b_mux[] = {
+	AVB0_AVTP_CAPTURE_B_MARK,
+};
+
 /* - I2C -------------------------------------------------------------------- */
 static const unsigned int i2c0_pins[] = {
 	/* SCL, SDA */
@@ -1165,6 +1303,24 @@  enum {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(avb0_td),
+	SH_PFC_PIN_GROUP(avb0_rd),
+	SH_PFC_PIN_GROUP(avb0_tx_ctl),
+	SH_PFC_PIN_GROUP(avb0_rx_ctl),
+	SH_PFC_PIN_GROUP(avb0_txc),
+	SH_PFC_PIN_GROUP(avb0_rxc),
+	SH_PFC_PIN_GROUP(avb0_txcrefclk),
+	SH_PFC_PIN_GROUP(avb0_link),
+	SH_PFC_PIN_GROUP(avb0_magic),
+	SH_PFC_PIN_GROUP(avb0_phy_int),
+	SH_PFC_PIN_GROUP(avb0_mdc),
+	SH_PFC_PIN_GROUP(avb0_mdio),
+	SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
+	SH_PFC_PIN_GROUP(avb0_avtp_match_a),
+	SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
+	SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
+	SH_PFC_PIN_GROUP(avb0_avtp_match_b),
+	SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
 	SH_PFC_PIN_GROUP(i2c0),
 	SH_PFC_PIN_GROUP(i2c1),
 	SH_PFC_PIN_GROUP(i2c2_a),
@@ -1198,6 +1354,27 @@  enum {
 	SH_PFC_PIN_GROUP(scif_clk),
 };
 
+static const char * const avb0_groups[] = {
+	"avb0_td",
+	"avb0_rd",
+	"avb0_tx_ctl",
+	"avb0_rx_ctl",
+	"avb0_txc",
+	"avb0_rxc",
+	"avb0_txcrefclk",
+	"avb0_link",
+	"avb0_magic",
+	"avb0_phy_int",
+	"avb0_mdc",
+	"avb0_mdio",
+	"avb0_avtp_pps_a",
+	"avb0_avtp_match_a",
+	"avb0_avtp_capture_a",
+	"avb0_avtp_pps_b",
+	"avb0_avtp_match_b",
+	"avb0_avtp_capture_b",
+};
+
 static const char * const i2c0_groups[] = {
 	"i2c0",
 };
@@ -1262,6 +1439,7 @@  enum {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(avb0),
 	SH_PFC_FUNCTION(i2c0),
 	SH_PFC_FUNCTION(i2c1),
 	SH_PFC_FUNCTION(i2c2),