From patchwork Wed Aug 9 12:05:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 799726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-82927-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="ykiep+it"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xS98X278Dz9rxm for ; Wed, 9 Aug 2017 22:10:52 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=IBuZvU2oPQkogtrl2pzT9EJMVhPec2Y gdhAQyDGjG+/fanDFBi124mRRChIyaA7FHY2S27tIqwhTzADLZhvrkBYtrjkr1qy KIaSa08VELiDaM96bUc6M0/Wxa+pQ7HJ3v3I2ks9EGDY3vEUV5a21hSA5gJKaARM f59aSfpWVsVE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=3YU6DxFEZ8a/s05UfRRdYqlgQlI=; b=ykiep +itkbLLeY6IMRHzWrpoJlFfBh776bVfdszCmQCbQ9ZgQxE2zmKfKGI3jVPjNGz2u OnqyxjU/yyM8ky5wF/VzjO/Jw2y1tP/RSIYOnJVvgFGYTcJdJRoyTdAJcou40T3y W9schagBgN84pn7s09kDWCpEG8TG7jKi77COXU= Received: (qmail 124388 invoked by alias); 9 Aug 2017 12:07:49 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 124323 invoked by uid 89); 9 Aug 2017 12:07:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=contemporary, safest, Hx-languages-length:4460 X-HELO: foss.arm.com From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Ard Biesheuvel , Szabolcs Nagy , Richard Sandiford , kvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org, linux-arch@vger.kernel.org Subject: [PATCH 17/27] arm64/sve: Preserve SVE registers around EFI runtime service calls Date: Wed, 9 Aug 2017 13:05:23 +0100 Message-Id: <1502280338-23002-18-git-send-email-Dave.Martin@arm.com> In-Reply-To: <1502280338-23002-1-git-send-email-Dave.Martin@arm.com> References: <1502280338-23002-1-git-send-email-Dave.Martin@arm.com> The EFI runtime services ABI allows EFI to make free use of the FPSIMD registers during EFI runtime service calls, subject to the callee-save requirements of the AArch64 procedure call standard. However, the SVE architecture allows upper bits of the SVE vector registers to be zeroed as a side-effect of FPSIMD V-register writes. This means that the SVE vector registers must be saved in their entirety in order to avoid data loss: non-SVE-aware EFI implementations cannot restore them correctly. The non-IRQ case is already handled gracefully by kernel_neon_begin(). For the IRQ case, this patch allocates a suitable per-CPU stash buffer for the full SVE register state and uses it to preserve the affected registers around EFI calls. It is currently unclear how the EFI runtime services ABI will be clarified with respect to SVE, so it safest to assume that the predicate registers and FFR must be saved and restored too. No attempt is made to restore the restore the vector length after a call, for now. It is deemed rather insane for EFI to change it, and contemporary EFI implementations certainly won't. Signed-off-by: Dave Martin Reviewed-by: Ard Biesheuvel --- arch/arm64/kernel/fpsimd.c | 53 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index b7fb836..c727b47 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -120,12 +120,14 @@ int sve_max_vl = -1; /* Set of available vector lengths, as vq_to_bit(vq): */ static DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); static bool sve_vq_map_finalised; +static void __percpu *efi_sve_state; #else /* ! CONFIG_ARM64_SVE */ /* Dummy declaration for code that will be optimised out: */ extern DECLARE_BITMAP(sve_vq_map, SVE_VQ_MAX); extern bool sve_vq_map_finalised; +extern void __percpu *efi_sve_state; #endif /* ! CONFIG_ARM64_SVE */ @@ -416,6 +418,23 @@ int sve_verify_vq_map(void) return ret; } +static void __init sve_kernel_mode_neon_setup(void) +{ + if (!IS_ENABLED(CONFIG_KERNEL_MODE_NEON)) + return; + + /* + * alloc_percpu() warns and prints a backtrace if this goes wrong. + * This is evidence of a crippled system and we are returning void, + * so no attempt is made to handle this situation here. + */ + BUG_ON(!sve_vl_valid(sve_max_vl)); + efi_sve_state = __alloc_percpu( + SVE_SIG_REGS_SIZE(sve_vq_from_vl(sve_max_vl)), 16); + if (!efi_sve_state) + panic("Cannot allocate percpu memory for EFI SVE save/restore"); +} + void __init sve_setup(void) { u64 zcr; @@ -455,6 +474,8 @@ void __init sve_setup(void) sve_max_vl); pr_info("SVE: default vector length %u bytes per vector\n", sve_default_vl); + + sve_kernel_mode_neon_setup(); } void fpsimd_release_thread(struct task_struct *dead_task) @@ -797,6 +818,7 @@ EXPORT_SYMBOL(kernel_neon_end); DEFINE_PER_CPU(struct fpsimd_state, efi_fpsimd_state); DEFINE_PER_CPU(bool, efi_fpsimd_state_used); +DEFINE_PER_CPU(bool, efi_sve_state_used); /* * EFI runtime services support functions @@ -825,7 +847,20 @@ void __efi_fpsimd_begin(void) if (may_use_simd()) kernel_neon_begin(); else { - fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); + /* + * If !efi_sve_state, SVE can't be in use yet and doesn't need + * preserving: + */ + if (system_supports_sve() && likely(efi_sve_state)) { + char *sve_state = this_cpu_ptr(efi_sve_state); + + __this_cpu_write(efi_sve_state_used, true); + + sve_save_state(sve_state + sve_ffr_offset(sve_max_vl), + &this_cpu_ptr(&efi_fpsimd_state)->fpsr); + } else + fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state)); + __this_cpu_write(efi_fpsimd_state_used, true); } } @@ -838,10 +873,20 @@ void __efi_fpsimd_end(void) if (!system_supports_fpsimd()) return; - if (__this_cpu_xchg(efi_fpsimd_state_used, false)) - fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); - else + if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) kernel_neon_end(); + else + if (system_supports_sve() && + likely(__this_cpu_read(efi_sve_state_used))) { + char const *sve_state = this_cpu_ptr(efi_sve_state); + + sve_load_state(sve_state + sve_ffr_offset(sve_max_vl), + &this_cpu_ptr(&efi_fpsimd_state)->fpsr, + sve_vq_from_vl(sve_get_vl()) - 1); + + __this_cpu_write(efi_sve_state_used, false); + } else + fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state)); } #endif /* CONFIG_KERNEL_MODE_NEON */