From patchwork Wed Aug 9 10:00:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Jiachai X-Patchwork-Id: 799607 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xS6HS6Rsrz9sN5 for ; Wed, 9 Aug 2017 20:01:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752761AbdHIKA7 (ORCPT ); Wed, 9 Aug 2017 06:00:59 -0400 Received: from regular1.263xmail.com ([211.150.99.132]:32833 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752233AbdHIKA5 (ORCPT ); Wed, 9 Aug 2017 06:00:57 -0400 Received: from hjc?rock-chips.com (unknown [192.168.167.12]) by regular1.263xmail.com (Postfix) with ESMTP id 9846A95B1; Wed, 9 Aug 2017 18:00:53 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 289BB360; Wed, 9 Aug 2017 18:00:53 +0800 (CST) X-RL-SENDER: hjc@rock-chips.com X-FST-TO: mark.yao@rock-chips.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: hjc@rock-chips.com X-UNIQUE-TAG: <4212113cc77cc5e485ac259e3624ad37> X-ATTACHMENT-NUM: 0 X-SENDER: hjc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 20807R1LY1R; Wed, 09 Aug 2017 18:00:54 +0800 (CST) From: Sandy Huang To: Mark Yao , David Airlie , Rob Herring , Mark Rutland , Heiko Stuebner Cc: Sandy Huang , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: display: Add Document for Rockchip Soc LVDS Date: Wed, 9 Aug 2017 18:00:49 +0800 Message-Id: <1502272851-63997-1-git-send-email-hjc@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1502272846-63941-1-git-send-email-hjc@rock-chips.com> References: <1502272846-63941-1-git-send-email-hjc@rock-chips.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch add Document for Rockchip Soc RK3288 LVDS, This based on the patches from Mark yao and Heiko Stuebner. Signed-off-by: Sandy Huang Signed-off-by: Mark yao Signed-off-by: Heiko Stuebner --- .../bindings/display/rockchip/rockchip-lvds.txt | 104 +++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt new file mode 100644 index 0000000..bf934ba --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt @@ -0,0 +1,104 @@ +Rockchip RK3288 LVDS interface +================================ + +Required properties: +- compatible: matching the soc type, one of + - "rockchip,rk3288-lvds"; + +- reg: physical base address of the controller and length + of memory mapped region. +- clocks: must include clock specifiers corresponding to entries in the + clock-names property. +- clock-names: must contain "pclk_lvds" + +- avdd1v0-supply: regulator phandle for 1.0V analog power +- avdd1v8-supply: regulator phandle for 1.8V analog power +- avdd3v3-supply: regulator phandle for 3.3V analog power + +- rockchip,grf: phandle to the general register files syscon + +Optional properties +- pinctrl-names: must contain a "lcdc" entry. +- pinctrl-0: pin control group to be used for this controller. + +Required nodes: + +The lvds has two video ports as described by + Documentation/devicetree/bindings/media/video-interfaces.txt. +Their connections are modeled using the OF graph bindings specified in + Documentation/devicetree/bindings/graph.txt. + +- video port 0 for the VOP inputs +- video port 1 for either a panel or subsequent encoder + +the lvds panel described by + Documentation/devicetree/bindings/display/panel/simple-panel.txt + +- rockchip,data-mapping: should be "vesa" or "jeida", + This describes how the color bits are laid out in the + serialized LVDS signal. +- rockchip,data-width : should be <18> or <24>; +- rockchip,output: should be "rgb", "lvds" or "duallvds", + This describes the output face. +- ports for remote LVDS output + +Example: + +lvds_panel: lvds-panel { + status = "okay"; + compatible = "simple-panel"; + enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>; + rockchip,data-mapping = "jeida"; + rockchip,data-width = <24>; + rockchip,output = "rgb"; + + ports { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; +}; + + +For Rockchip RK3288: + + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; + rockchip,grf = <&grf>; + reg = <0xff96c000 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk_lvds"; + pinctrl-names = "lcdc"; + pinctrl-0 = <&lcdc_ctl>; + avdd1v0-supply = <&vdd10_lcd>; + avdd1v8-supply = <&vcc18_lcd>; + avdd3v3-supply = <&vcca_33>; + rockchip,data-mapping = "jeida"; + rockchip,data-width = <24>; + rockchip,output = "rgb"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + lvds_in: port@0 { + reg = <0>; + + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + lvds_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; + + lvds_out: port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + };