powerpc: Restrict xssqrtqp operands to Vector Registers (Altivec/VMX)

Message ID 20170808161232.17066-1-gftg@linux.vnet.ibm.com
State New
Headers show

Commit Message

Gabriel F. T. Gomes Aug. 8, 2017, 4:12 p.m.
POWER ISA 3.0 introduces the xssqrtqp instructions, which expects
operands to be in Vector Registers (Altivec/VMX), even though this
instruction belongs to the Vector-Scalar Instruction Set.

In GCC's Extended Assembly for POWER, the 'wq' register constraint is
provided for use with IEEE 754 128-bit floating-point values.  However,
this constrain does not limit the register allocation to Vector
Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX)
to the operands of the instruction.

This patch changes the register constraint used in sqrtf128 from 'wq' to
'v', in order to request a Vector Register (Altivec/VMX) for use with
the xssqrtqp instruction.

Tested for powerpc64le and --with-cpu=power9.

	* sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since
	xssqrtqp requires operands to be in Vector Registers
	(Altivec/VMX), replace the register constraint 'wq' with 'v'.
	* sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
	(__ieee754_sqrtf128): Likewise.
---
 sysdeps/powerpc/fpu/math_private.h                  | 2 +-
 sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

Comments

Alan Modra Aug. 9, 2017, 8:52 a.m. | #1
On Tue, Aug 08, 2017 at 01:12:32PM -0300, Gabriel F. T. Gomes wrote:
> 	* sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since
> 	xssqrtqp requires operands to be in Vector Registers
> 	(Altivec/VMX), replace the register constraint 'wq' with 'v'.
> 	* sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
> 	(__ieee754_sqrtf128): Likewise.

Looks good.
Tulio Magno Quites Machado Filho Aug. 9, 2017, 2:49 p.m. | #2
"Gabriel F. T. Gomes" <gftg@linux.vnet.ibm.com> writes:

> POWER ISA 3.0 introduces the xssqrtqp instructions, which expects
> operands to be in Vector Registers (Altivec/VMX), even though this
> instruction belongs to the Vector-Scalar Instruction Set.
>
> In GCC's Extended Assembly for POWER, the 'wq' register constraint is
> provided for use with IEEE 754 128-bit floating-point values.  However,
> this constrain does not limit the register allocation to Vector

s/constrain/constraint/

> Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX)
> to the operands of the instruction.
>
> This patch changes the register constraint used in sqrtf128 from 'wq' to
> 'v', in order to request a Vector Register (Altivec/VMX) for use with
> the xssqrtqp instruction.
>
> Tested for powerpc64le and --with-cpu=power9.
>
> 	* sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since
> 	xssqrtqp requires operands to be in Vector Registers
> 	(Altivec/VMX), replace the register constraint 'wq' with 'v'.
> 	* sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
> 	(__ieee754_sqrtf128): Likewise.

Looks good to me, but as it affects glibc 2.26, I think we need a bug report
and a bugzilla number in the commit message.

Thanks!
Gabriel F. T. Gomes Aug. 11, 2017, 12:50 p.m. | #3
On Wed, 09 Aug 2017 11:49:24 -0300
"Tulio Magno Quites Machado Filho" <tuliom@linux.vnet.ibm.com> wrote:

> Looks good to me, but as it affects glibc 2.26, I think we need a bug report
> and a bugzilla number in the commit message.

Thanks, I created the bugzilla entry and pushed this patch with the
changes.

Patch

diff --git a/sysdeps/powerpc/fpu/math_private.h b/sysdeps/powerpc/fpu/math_private.h
index d8fd4923ac..396fd0562e 100644
--- a/sysdeps/powerpc/fpu/math_private.h
+++ b/sysdeps/powerpc/fpu/math_private.h
@@ -30,7 +30,7 @@  extern __always_inline _Float128
 __ieee754_sqrtf128 (_Float128 __x)
 {
   _Float128 __z;
-  asm ("xssqrtqp %0,%1" : "=wq" (__z) : "wq" (__x));
+  asm ("xssqrtqp %0,%1" : "=v" (__z) : "v" (__x));
   return __z;
 }
 #endif
diff --git a/sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c b/sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
index 769d3f8922..59fd8269f5 100644
--- a/sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
+++ b/sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c
@@ -30,7 +30,7 @@  __float128
 __ieee754_sqrtf128 (__float128 a)
 {
   __float128 z;
-  asm ("xssqrtqp %0,%1" : "=wq" (z) : "wq" (a));
+  asm ("xssqrtqp %0,%1" : "=v" (z) : "v" (a));
   return z;
 }
 strong_alias (__ieee754_sqrtf128, __sqrtf128_finite)