From patchwork Thu Jan 20 21:36:42 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 79772 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id B98F7B7105 for ; Fri, 21 Jan 2011 08:37:20 +1100 (EST) Received: (qmail 28832 invoked by alias); 20 Jan 2011 21:37:18 -0000 Received: (qmail 28822 invoked by uid 22791); 20 Jan 2011 21:37:17 -0000 X-SWARE-Spam-Status: No, hits=-2.4 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, RFC_ABUSE_POST X-Spam-Check-By: sourceware.org Received: from mail-fx0-f47.google.com (HELO mail-fx0-f47.google.com) (209.85.161.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 20 Jan 2011 21:37:12 +0000 Received: by fxm17 with SMTP id 17so1094420fxm.20 for ; Thu, 20 Jan 2011 13:37:10 -0800 (PST) MIME-Version: 1.0 Received: by 10.223.95.203 with SMTP id e11mr2614984fan.60.1295559402435; Thu, 20 Jan 2011 13:36:42 -0800 (PST) Received: by 10.223.70.129 with HTTP; Thu, 20 Jan 2011 13:36:42 -0800 (PST) Date: Thu, 20 Jan 2011 21:36:42 +0000 Message-ID: Subject: [Patch wwwdocs] Update docs with respect to changes for ARM. From: Ramana Radhakrishnan To: gcc-patches Cc: Richard Earnshaw , gerald@pfeifer.com X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, I think I've managed to scrub together all the relevant changes for ARM for the past year and here's a patch that reflects it. I am slightly suspicious of the wording I've put together for the fstrict-volatile-bitfields option and that's the one thing that I'd like some review on. cheers Ramana Index: ./htdocs/gcc-4.6/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.6/changes.html,v retrieving revision 1.90 diff -a -u -r1.90 changes.html --- ./htdocs/gcc-4.6/changes.html 17 Jan 2011 01:55:22 -0000 1.90 +++ ./htdocs/gcc-4.6/changes.html 20 Jan 2011 21:35:29 -0000 @@ -568,8 +568,43 @@

ARM

    -
  • The SSA loop prefetching pass is enabled when - using -O3.
    • +
  • GCC now supports the Cortex-M4 processor implementing + the v7-em version of the architecture using the option + -mcpu=cortex-m4.
    • + +
  • Scheduling descriptions for the Cortex-M4, the Neon and + the Floating point units of the Cortex-A9 and a pipeline + description for the Cortex-A5 have been added.
    • + +
  • Synchronization primitives such as __sync_fetch_and_add + and friends are now inlined for supported architectures + rather than calling into a kernel helper function.
    • + +
  • SSA loop prefetching is enabled by default for the + Cortex-A9 at -O3.
    • + +
  • Several improvements were submitted to improve code + generation for the ARM architecture including a rewritten + implementation for load and store multiples.
    • + +
  • Several enhancements were submitted to improve SIMD code + generation for NEON by adding support for widening instructions, + misaligned loads and stores, vector conditionals and + support for 64 bit arithmetic.
    • + +
  • Support was added for the Faraday cores fa526, fa606te, + fa626te, fmp626te, fmp626 and fa726te and can be used with the + respective names as parameters to the -mcpu= + option.
    • + +
  • Basic support was added for Cortex A15 and is available through + -mcpu=cortex-a15.
    • + +
  • The command line option -fstrict-volatile-bitfields + has been turned on by default for AAPCS configurations whereby volatile + bitfield members of aggregates are accessed by a single access of the + width of the field's type, aligned to a natural alignment if possible. +

IA-32/x86-64