Patchwork [wwwdocs] Update docs with respect to changes for ARM.

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Submitter Ramana Radhakrishnan
Date Jan. 20, 2011, 9:36 p.m.
Message ID <AANLkTinhxN8BfyOEeLdhGrvc+w7+qXu-FKxFOON4eXXf@mail.gmail.com>
Download mbox | patch
Permalink /patch/79772/
State New
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Comments

Ramana Radhakrishnan - Jan. 20, 2011, 9:36 p.m.
Hi,

I think I've managed to scrub together all the relevant changes for
ARM for the past year and here's a patch that reflects it. I am
slightly suspicious of the wording I've put together for the
fstrict-volatile-bitfields option and that's the one thing that I'd
like some review on.


cheers
Ramana
Ramana Radhakrishnan - Jan. 26, 2011, 11:48 a.m.
Ping.

http://gcc.gnu.org/ml/gcc-patches/2011-01/msg01423.html

Ramana

On Thu, 2011-01-20 at 21:36 +0000, Ramana Radhakrishnan wrote:
> Hi,
> 
> I think I've managed to scrub together all the relevant changes for
> ARM for the past year and here's a patch that reflects it. I am
> slightly suspicious of the wording I've put together for the
> fstrict-volatile-bitfields option and that's the one thing that I'd
> like some review on.
> 
> 
> cheers
> Ramana
Richard Earnshaw - Jan. 26, 2011, 3:02 p.m.
On Thu, 2011-01-20 at 21:36 +0000, Ramana Radhakrishnan wrote:
> Hi,
> 
> I think I've managed to scrub together all the relevant changes for
> ARM for the past year and here's a patch that reflects it. I am
> slightly suspicious of the wording I've put together for the
> fstrict-volatile-bitfields option and that's the one thing that I'd
> like some review on.
> 
> 
> cheers
> Ramana

+    <li>Several improvements were submitted to improve code 
+      generation for the ARM architecture including a rewritten 
+      implementation for load and store multiples.</li>

Submitted? or Committed?  I'd suggest

        <li>Improvements to code generation for the ARM architecture,
        including a rewritten...

+    <li>Several enhancements were submitted to improve SIMD code 
+      generation for NEON by adding support for widening instructions, 
+      misaligned loads and stores, vector conditionals and 
+      support for 64 bit arithmetic.</li>

likewise.

+    <li> The command line option <code>-fstrict-volatile-bitfields</code> 
+      has been turned on by default for AAPCS configurations whereby volatile
+      bitfield members of aggregates are accessed by a single access of the
+      width of the field's type, aligned to a natural alignment if possible.

I'd suggest here:

        <li> GCC for AAPCS configurations now more closely adheres to
        the AAPCS specification by enabling
        <code>-fstrict-volatile-bitfields</code> by default.
        
R.
Gerald Pfeifer - Jan. 26, 2011, 10:55 p.m.
On Thu, 20 Jan 2011, Ramana Radhakrishnan wrote:
> I think I've managed to scrub together all the relevant changes for
> ARM for the past year and here's a patch that reflects it.

Nice job!  Given how specific this is to ARM I'd like to defer the
actual refer to Richard who has done this now. :-)

From my side, only one most minor note:

Index: ./htdocs/gcc-4.6/changes.html
===================================================================
+    <li>Scheduling descriptions for the Cortex-M4, the Neon and 
+      the Floating point units of the Cortex-A9 and a pipeline 
+      description for the Cortex-A5 have been added.</li>

"floating point units" (lower case F)?

If Richard is fine, please apply.

Thanks,
Gerald
Richard Earnshaw - Jan. 27, 2011, 12:10 a.m.
Ok with the various suggested changes.

R.



On 26 Jan 2011, at 22:55, "Gerald Pfeifer" <gerald@pfeifer.com> wrote:

> On Thu, 20 Jan 2011, Ramana Radhakrishnan wrote:
>> I think I've managed to scrub together all the relevant changes for
>> ARM for the past year and here's a patch that reflects it.
> 
> Nice job!  Given how specific this is to ARM I'd like to defer the
> actual refer to Richard who has done this now. :-)
> 
> From my side, only one most minor note:
> 
> Index: ./htdocs/gcc-4.6/changes.html
> ===================================================================
> +    <li>Scheduling descriptions for the Cortex-M4, the Neon and 
> +      the Floating point units of the Cortex-A9 and a pipeline 
> +      description for the Cortex-A5 have been added.</li>
> 
> "floating point units" (lower case F)?
> 
> If Richard is fine, please apply.
> 
> Thanks,
> Gerald
>

Patch

Index: ./htdocs/gcc-4.6/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.6/changes.html,v
retrieving revision 1.90
diff -a -u -r1.90 changes.html
--- ./htdocs/gcc-4.6/changes.html	17 Jan 2011 01:55:22 -0000	1.90
+++ ./htdocs/gcc-4.6/changes.html	20 Jan 2011 21:35:29 -0000
@@ -568,8 +568,43 @@ 
 
 <h3 id="arm">ARM</h3>
   <ul>
-    <li>The SSA loop prefetching pass is enabled when
-      using <code>-O3</code>.</li>
+    <li>GCC now supports the Cortex-M4 processor implementing 
+      the v7-em version of the architecture using the option
+      <code>-mcpu=cortex-m4</code>.</li>
+
+    <li>Scheduling descriptions for the Cortex-M4, the Neon and 
+      the Floating point units of the Cortex-A9 and a pipeline 
+      description for the Cortex-A5 have been added.</li>
+
+    <li>Synchronization primitives such as <code>__sync_fetch_and_add
+      </code> and friends are now inlined for supported architectures
+      rather than calling into a kernel helper function.</li>
+
+    <li>SSA loop prefetching is enabled by default for the 
+      Cortex-A9 at <code>-O3</code>.</li>
+
+    <li>Several improvements were submitted to improve code 
+      generation for the ARM architecture including a rewritten 
+      implementation for load and store multiples.</li>
+
+    <li>Several enhancements were submitted to improve SIMD code 
+      generation for NEON by adding support for widening instructions, 
+      misaligned loads and stores, vector conditionals and 
+      support for 64 bit arithmetic.</li>
+
+    <li>Support was added for the Faraday cores fa526, fa606te, 
+      fa626te, fmp626te, fmp626 and fa726te and can be used with the
+      respective names as parameters to the <code>-mcpu=</code> 
+      option.</li>
+
+    <li> Basic support was added for Cortex A15 and is available through 
+      <code>-mcpu=cortex-a15</code>.</li>
+    
+    <li> The command line option <code>-fstrict-volatile-bitfields</code> 
+      has been turned on by default for AAPCS configurations whereby volatile
+      bitfield members of aggregates are accessed by a single access of the
+      width of the field's type, aligned to a natural alignment if possible.
+      </li>
   </ul>
 
 <h3>IA-32/x86-64</h3>