| Message ID | 1501760922-14079-1-git-send-email-w.egorov@phytec.de |
|---|---|
| State | Changes Requested |
| Delegated to: | Philipp Tomsich |
| Headers | show |
> Sometimes it's helpful to know the reset reason caused in the SoC. > Add reset reason detection for the RK3288 SoC. > This will set an environment variable which represents the reset reason. > > Signed-off-by: Wadim Egorov <w.egorov@phytec.de> > --- > Changes in v3: > - Fixed typo in commit message > - Use enum for CRU_GLB_RST_ST register decoding > > --- > arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 12 +++++++++ > arch/arm/mach-rockchip/rk3288-board.c | 35 +++++++++++++++++++++++++ > 2 files changed, 47 insertions(+) > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On Thu, 3 Aug 2017, Wadim Egorov wrote: > Sometimes it's helpful to know the reset reason caused in the SoC. > Add reset reason detection for the RK3288 SoC. > This will set an environment variable which represents the reset reason. > > Signed-off-by: Wadim Egorov <w.egorov@phytec.de> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > Changes in v3: > - Fixed typo in commit message > - Use enum for CRU_GLB_RST_ST register decoding The changes requested by Simon are still pending. Plus a few more comments from me below... > > --- > arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 12 +++++++++ > arch/arm/mach-rockchip/rk3288-board.c | 35 +++++++++++++++++++++++++ > 2 files changed, 47 insertions(+) > > diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h > index cb0a935..a52986b 100644 > --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h > +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h > @@ -220,4 +220,16 @@ enum { > CLKF_MASK = 0x1fff << CLKF_SHIFT, GENMASK? > }; > > +/* CRU_GLB_RST_ST */ > +enum { > + GLB_POR_RST, > + FST_GLB_RST_ST, > + SND_GLB_RST_ST, Shouldn't SND_GLB_RST_ST be BIT(1)? > + FST_GLB_TSADC_RST_ST = 0x4, > + SND_GLB_TSADC_RST_ST = 0x8, > + FST_GLB_WDT_RST_ST = 0x10, > + SND_GLB_WDT_RST_ST = 0x20, BIT(...)? > + GLB_RST_ST_MASK = 0x3f, > +}; > + > #endif > diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c > index 613967c..1ac70ff 100644 > --- a/arch/arm/mach-rockchip/rk3288-board.c > +++ b/arch/arm/mach-rockchip/rk3288-board.c > @@ -11,6 +11,7 @@ > #include <syscon.h> > #include <asm/io.h> > #include <asm/arch/clock.h> > +#include <asm/arch/cru_rk3288.h> > #include <asm/arch/periph.h> > #include <asm/arch/pmu_rk3288.h> > #include <asm/arch/qos_rk3288.h> > @@ -70,10 +71,44 @@ int rk3288_qos_init(void) > return 0; > } > > +static void rk3288_detect_reset_reason(void) > +{ > + struct rk3288_cru *cru = rockchip_get_cru(); > + if (IS_ERR(cru)) > + return; > + > + switch (cru->cru_glb_rst_st) { > + case GLB_POR_RST: > + setenv("reset_reason", "POR"); > + break; > + case FST_GLB_RST_ST: > + case SND_GLB_RST_ST: > + setenv("reset_reason", "RST"); > + break; > + case FST_GLB_TSADC_RST_ST: > + case SND_GLB_TSADC_RST_ST: > + setenv("reset_reason", "THERMAL"); > + break; > + case FST_GLB_WDT_RST_ST: > + case SND_GLB_WDT_RST_ST: > + setenv("reset_reason", "WDOG"); > + break; > + default: > + setenv("reset_reason", "unknown reset"); > + } > + > + /* > + * Clear cru_glb_rst_st, so we can determine the last reset cause > + * for following resets. > + */ > + rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); > +} > + > int board_late_init(void) > { > setup_boot_mode(); > rk3288_qos_init(); > + rk3288_detect_reset_reason(); > > return rk_board_late_init(); > } >
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index cb0a935..a52986b 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -220,4 +220,16 @@ enum { CLKF_MASK = 0x1fff << CLKF_SHIFT, }; +/* CRU_GLB_RST_ST */ +enum { + GLB_POR_RST, + FST_GLB_RST_ST, + SND_GLB_RST_ST, + FST_GLB_TSADC_RST_ST = 0x4, + SND_GLB_TSADC_RST_ST = 0x8, + FST_GLB_WDT_RST_ST = 0x10, + SND_GLB_WDT_RST_ST = 0x20, + GLB_RST_ST_MASK = 0x3f, +}; + #endif diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 613967c..1ac70ff 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -11,6 +11,7 @@ #include <syscon.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/cru_rk3288.h> #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3288.h> #include <asm/arch/qos_rk3288.h> @@ -70,10 +71,44 @@ int rk3288_qos_init(void) return 0; } +static void rk3288_detect_reset_reason(void) +{ + struct rk3288_cru *cru = rockchip_get_cru(); + if (IS_ERR(cru)) + return; + + switch (cru->cru_glb_rst_st) { + case GLB_POR_RST: + setenv("reset_reason", "POR"); + break; + case FST_GLB_RST_ST: + case SND_GLB_RST_ST: + setenv("reset_reason", "RST"); + break; + case FST_GLB_TSADC_RST_ST: + case SND_GLB_TSADC_RST_ST: + setenv("reset_reason", "THERMAL"); + break; + case FST_GLB_WDT_RST_ST: + case SND_GLB_WDT_RST_ST: + setenv("reset_reason", "WDOG"); + break; + default: + setenv("reset_reason", "unknown reset"); + } + + /* + * Clear cru_glb_rst_st, so we can determine the last reset cause + * for following resets. + */ + rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); +} + int board_late_init(void) { setup_boot_mode(); rk3288_qos_init(); + rk3288_detect_reset_reason(); return rk_board_late_init(); }
Sometimes it's helpful to know the reset reason caused in the SoC. Add reset reason detection for the RK3288 SoC. This will set an environment variable which represents the reset reason. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> --- Changes in v3: - Fixed typo in commit message - Use enum for CRU_GLB_RST_ST register decoding --- arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 12 +++++++++ arch/arm/mach-rockchip/rk3288-board.c | 35 +++++++++++++++++++++++++ 2 files changed, 47 insertions(+)