[PATCHv2,2/6] PCI: designware: enable write permission before updating class code

Submitted by Zhiqiang Hou on Aug. 3, 2017, 8:23 a.m.

Details

Message ID 1501748620-42866-3-git-send-email-Zhiqiang.Hou@nxp.com
State Changes Requested
Headers show

Commit Message

Zhiqiang Hou Aug. 3, 2017, 8:23 a.m.
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The existing fix doesn't actually work because the Class register is
read-only, so it must enable the write permission before write the
correct value to this register.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
 - None

 drivers/pci/dwc/pcie-designware-host.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Joao Pinto Aug. 8, 2017, 12:45 p.m.
Às 9:23 AM de 8/3/2017, Zhiqiang Hou escreveu:
> From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> 
> The existing fix doesn't actually work because the Class register is
> read-only, so it must enable the write permission before write the
> correct value to this register.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> ---
> V2:
>  - None
> 
>  drivers/pci/dwc/pcie-designware-host.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index d29c020..6e10cda 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -634,8 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
>  
>  	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
>  
> +	/* Enable write permission for the DBI read-only register */
> +	dw_pcie_dbi_ro_wr_en(pci);
>  	/* program correct class for RC */
>  	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
> +	/* Better disable write permission right after the update */
> +	dw_pcie_dbi_ro_wr_dis(pci);
>  
>  	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
>  	val |= PORT_LOGIC_SPEED_CHANGE;
> 

Acked-By: Joao Pinto <jpinto@synopsys.com>
Zhiqiang Hou Aug. 9, 2017, 2:51 a.m.
Hi Joao,

Thanks a lot for your ack!

> -----Original Message-----

> From: Joao Pinto [mailto:Joao.Pinto@synopsys.com]

> Sent: 2017年8月8日 20:46

> To: Z.q. Hou <zhiqiang.hou@nxp.com>; linux-pci@vger.kernel.org;

> bhelgaas@google.com; jingoohan1@gmail.com; Joao.Pinto@synopsys.com

> Cc: M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>;

> Roy Zang <roy.zang@nxp.com>

> Subject: Re: [PATCHv2 2/6] PCI: designware: enable write permission before

> updating class code

> 

> Às 9:23 AM de 8/3/2017, Zhiqiang Hou escreveu:

> > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

> >

> > The existing fix doesn't actually work because the Class register is

> > read-only, so it must enable the write permission before write the

> > correct value to this register.

> >

> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

> > ---

> > V2:

> >  - None

> >

> >  drivers/pci/dwc/pcie-designware-host.c | 4 ++++

> >  1 file changed, 4 insertions(+)

> >

> > diff --git a/drivers/pci/dwc/pcie-designware-host.c

> > b/drivers/pci/dwc/pcie-designware-host.c

> > index d29c020..6e10cda 100644

> > --- a/drivers/pci/dwc/pcie-designware-host.c

> > +++ b/drivers/pci/dwc/pcie-designware-host.c

> > @@ -634,8 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)

> >

> >  	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);

> >

> > +	/* Enable write permission for the DBI read-only register */

> > +	dw_pcie_dbi_ro_wr_en(pci);

> >  	/* program correct class for RC */

> >  	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2,

> PCI_CLASS_BRIDGE_PCI);

> > +	/* Better disable write permission right after the update */

> > +	dw_pcie_dbi_ro_wr_dis(pci);

> >

> >  	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4,

> &val);

> >  	val |= PORT_LOGIC_SPEED_CHANGE;

> >

> 

> Acked-By: Joao Pinto <jpinto@synopsys.com>


- Zhiqiang

Patch hide | download patch | download mbox

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index d29c020..6e10cda 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -634,8 +634,12 @@  void dw_pcie_setup_rc(struct pcie_port *pp)
 
 	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 
+	/* Enable write permission for the DBI read-only register */
+	dw_pcie_dbi_ro_wr_en(pci);
 	/* program correct class for RC */
 	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+	/* Better disable write permission right after the update */
+	dw_pcie_dbi_ro_wr_dis(pci);
 
 	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 	val |= PORT_LOGIC_SPEED_CHANGE;