Message ID | 1501706105-7490-58-git-send-email-philipp.tomsich@theobroma-systems.com |
---|---|
State | Accepted |
Delegated to: | Philipp Tomsich |
Headers | show |
> For the RK3368, we can reuse the SPI driver (although we'll have to > eventually investigate whether it can be merged with the > designware_spi.c driver) also used for the RK3288 and RK3399. > This adds the necessary compatible string to support the RK3368. > > Note that the assumption that GPLL will be clocked at 594MHz is not > true for the RK3368, but this will not lead to incorrect functioning > (just to a lower-than-expected SPI operating frequency): this has been > documented in the driver, so it doesn't cause any headaches when > someone next needs to touch the clock code of this driver. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > > Version-changes: 2 > - added in this version > > Reviewed-by: Simon Glass <sjg@chromium.org> > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > drivers/spi/rk_spi.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > Applied to u-boot-rockchip, thanks!
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 7921ea0..c70d636 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -210,6 +210,14 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) static int rockchip_spi_calc_modclk(ulong max_freq) { + /* + * While this is not strictly correct for the RK3368, as the + * GPLL will be 576MHz, things will still work, as the + * clk_set_rate(...) implementation in our clock-driver will + * chose the next closest rate not exceeding what we request + * based on the output of this function. + */ + unsigned div; const unsigned long gpll_hz = 594000000UL; @@ -443,6 +451,7 @@ static const struct dm_spi_ops rockchip_spi_ops = { static const struct udevice_id rockchip_spi_ids[] = { { .compatible = "rockchip,rk3288-spi" }, + { .compatible = "rockchip,rk3368-spi" }, { .compatible = "rockchip,rk3399-spi" }, { } };