diff mbox

[U-Boot,v3,36/66] rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver

Message ID 1501269764-13969-37-git-send-email-philipp.tomsich@theobroma-systems.com
State Superseded
Delegated to: Philipp Tomsich
Headers show

Commit Message

Philipp Tomsich July 28, 2017, 7:22 p.m. UTC 
There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).

This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Simon Glass <sjg@chromium.org>
---

Changes in v3: None
Changes in v2:
- moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX
  definitions) to the rk3368 pinctrl driver implementation

 arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 316 -----------------------
 drivers/pinctrl/rockchip/pinctrl_rk3368.c       | 325 ++++++++++++++++++++++++
 2 files changed, 325 insertions(+), 316 deletions(-)
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index 1966960..ec42d7a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -100,322 +100,6 @@  struct rk3368_pmu_grf {
 check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
 check_member(rk3368_pmu_grf, os_reg[0], 0x200);
 
-/*GRF_GPIO0C_IOMUX*/
-enum {
-	GPIO0C7_MASK	       = GENMASK(15, 14),
-	GPIO0C7_GPIO	       = 0,
-	GPIO0C7_LCDC_D19        = (1 << 14),
-	GPIO0C7_TRACE_D9        = (2 << 14),
-	GPIO0C7_UART1_RTSN      = (3 << 14),
-
-	GPIO0C6_MASK            = GENMASK(13, 12),
-	GPIO0C6_GPIO            = 0,
-	GPIO0C6_LCDC_D18        = (1 << 12),
-	GPIO0C6_TRACE_D8        = (2 << 12),
-	GPIO0C6_UART1_CTSN      = (3 << 12),
-
-	GPIO0C5_MASK            = GENMASK(11, 10),
-	GPIO0C5_GPIO            = 0,
-	GPIO0C5_LCDC_D17        = (1 << 10),
-	GPIO0C5_TRACE_D7        = (2 << 10),
-	GPIO0C5_UART1_SOUT      = (3 << 10),
-
-	GPIO0C4_MASK            = GENMASK(9, 8),
-	GPIO0C4_GPIO            = 0,
-	GPIO0C4_LCDC_D16        = (1 << 8),
-	GPIO0C4_TRACE_D6        = (2 << 8),
-	GPIO0C4_UART1_SIN       = (3 << 8),
-
-	GPIO0C3_MASK            = GENMASK(7, 6),
-	GPIO0C3_GPIO            = 0,
-	GPIO0C3_LCDC_D15        = (1 << 6),
-	GPIO0C3_TRACE_D5        = (2 << 6),
-	GPIO0C3_MCU_JTAG_TDO    = (3 << 6),
-
-	GPIO0C2_MASK            = GENMASK(5, 4),
-	GPIO0C2_GPIO            = 0,
-	GPIO0C2_LCDC_D14        = (1 << 4),
-	GPIO0C2_TRACE_D4        = (2 << 4),
-	GPIO0C2_MCU_JTAG_TDI    = (3 << 4),
-
-	GPIO0C1_MASK            = GENMASK(3, 2),
-	GPIO0C1_GPIO            = 0,
-	GPIO0C1_LCDC_D13        = (1 << 2),
-	GPIO0C1_TRACE_D3        = (2 << 2),
-	GPIO0C1_MCU_JTAG_TRTSN  = (3 << 2),
-
-	GPIO0C0_MASK            = GENMASK(1, 0),
-	GPIO0C0_GPIO            = 0,
-	GPIO0C0_LCDC_D12        = (1 << 0),
-	GPIO0C0_TRACE_D2        = (2 << 0),
-	GPIO0C0_MCU_JTAG_TDO    = (3 << 0),
-};
-
-/*GRF_GPIO0D_IOMUX*/
-enum {
-	GPIO0D7_MASK            = GENMASK(15, 14),
-	GPIO0D7_GPIO            = 0,
-	GPIO0D7_LCDC_DCLK       = (1 << 14),
-	GPIO0D7_TRACE_CTL       = (2 << 14),
-	GPIO0D7_PMU_DEBUG5      = (3 << 14),
-
-	GPIO0D6_MASK            = GENMASK(13, 12),
-	GPIO0D6_GPIO            = 0,
-	GPIO0D6_LCDC_DEN        = (1 << 12),
-	GPIO0D6_TRACE_CLK       = (2 << 12),
-	GPIO0D6_PMU_DEBUG4      = (3 << 12),
-
-	GPIO0D5_MASK            = GENMASK(11, 10),
-	GPIO0D5_GPIO            = 0,
-	GPIO0D5_LCDC_VSYNC             = (1 << 10),
-	GPIO0D5_TRACE_D15       = (2 << 10),
-	GPIO0D5_PMU_DEBUG3      = (3 << 10),
-
-	GPIO0D4_MASK            = GENMASK(9, 8),
-	GPIO0D4_GPIO            = 0,
-	GPIO0D4_LCDC_HSYNC      = (1 << 8),
-	GPIO0D4_TRACE_D14       = (2 << 8),
-	GPIO0D4_PMU_DEBUG2      = (3 << 8),
-
-	GPIO0D3_MASK            = GENMASK(7, 6),
-	GPIO0D3_GPIO            = 0,
-	GPIO0D3_LCDC_D23        = (1 << 6),
-	GPIO0D3_TRACE_D13       = (2 << 6),
-	GPIO0D3_UART4_SIN       = (3 << 6),
-
-	GPIO0D2_MASK            = GENMASK(5, 4),
-	GPIO0D2_GPIO            = 0,
-	GPIO0D2_LCDC_D22        = (1 << 4),
-	GPIO0D2_TRACE_D12       = (2 << 4),
-	GPIO0D2_UART4_SOUT      = (3 << 4),
-
-	GPIO0D1_MASK            = GENMASK(3, 2),
-	GPIO0D1_GPIO            = 0,
-	GPIO0D1_LCDC_D21        = (1 << 2),
-	GPIO0D1_TRACE_D11       = (2 << 2),
-	GPIO0D1_UART4_RTSN      = (3 << 2),
-
-	GPIO0D0_MASK            = GENMASK(1, 0),
-	GPIO0D0_GPIO            = 0,
-	GPIO0D0_LCDC_D20        = (1 << 0),
-	GPIO0D0_TRACE_D10       = (2 << 0),
-	GPIO0D0_UART4_CTSN      = (3 << 0),
-};
-
-/*GRF_GPIO2A_IOMUX*/
-enum {
-	GPIO2A7_MASK            = GENMASK(15, 14),
-	GPIO2A7_GPIO            = 0,
-	GPIO2A7_SDMMC0_D2       = (1 << 14),
-	GPIO2A7_JTAG_TCK        = (2 << 14),
-
-	GPIO2A6_MASK            = GENMASK(13, 12),
-	GPIO2A6_GPIO            = 0,
-	GPIO2A6_SDMMC0_D1       = (1 << 12),
-	GPIO2A6_UART2_SIN       = (2 << 12),
-
-	GPIO2A5_MASK            = GENMASK(11, 10),
-	GPIO2A5_GPIO            = 0,
-	GPIO2A5_SDMMC0_D0       = (1 << 10),
-	GPIO2A5_UART2_SOUT      = (2 << 10),
-
-	GPIO2A4_MASK            = GENMASK(9, 8),
-	GPIO2A4_GPIO     = 0,
-	GPIO2A4_FLASH_DQS       = (1 << 8),
-	GPIO2A4_EMMC_CLKOUT     = (2 << 8),
-
-	GPIO2A3_MASK            = GENMASK(7, 6),
-	GPIO2A3_GPIO            = 0,
-	GPIO2A3_FLASH_CSN3      = (1 << 6),
-	GPIO2A3_EMMC_RSTNOUT    = (2 << 6),
-
-	GPIO2A2_MASK            = GENMASK(5, 4),
-	GPIO2A2_GPIO            = 0,
-	GPIO2A2_FLASH_CSN2      = (1 << 4),
-
-	GPIO2A1_MASK            = GENMASK(3, 2),
-	GPIO2A1_GPIO            = 0,
-	GPIO2A1_FLASH_CSN1      = (1 << 2),
-
-	GPIO2A0_MASK            = GENMASK(1, 0),
-	GPIO2A0_GPIO            = 0,
-	GPIO2A0_FLASH_CSN0      = (1 << 0),
-};
-
-/*GRF_GPIO2D_IOMUX*/
-enum {
-	GPIO2D7_MASK            = GENMASK(15, 14),
-	GPIO2D7_GPIO            = 0,
-	GPIO2D7_SDIO0_D3        = (1 << 14),
-
-	GPIO2D6_MASK            = GENMASK(13, 12),
-	GPIO2D6_GPIO            = 0,
-	GPIO2D6_SDIO0_D2        = (1 << 12),
-
-	GPIO2D5_MASK            = GENMASK(11, 10),
-	GPIO2D5_GPIO            = 0,
-	GPIO2D5_SDIO0_D1        = (1 << 10),
-
-	GPIO2D4_MASK            = GENMASK(9, 8),
-	GPIO2D4_GPIO            = 0,
-	GPIO2D4_SDIO0_D0        = (1 << 8),
-
-	GPIO2D3_MASK            = GENMASK(7, 6),
-	GPIO2D3_GPIO            = 0,
-	GPIO2D3_UART0_RTS0      = (1 << 6),
-
-	GPIO2D2_MASK            = GENMASK(5, 4),
-	GPIO2D2_GPIO            = 0,
-	GPIO2D2_UART0_CTS0      = (1 << 4),
-
-	GPIO2D1_MASK            = GENMASK(3, 2),
-	GPIO2D1_GPIO            = 0,
-	GPIO2D1_UART0_SOUT      = (1 << 2),
-
-	GPIO2D0_MASK            = GENMASK(1, 0),
-	GPIO2D0_GPIO            = 0,
-	GPIO2D0_UART0_SIN       = (1 << 0),
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
-	GPIO1C7_MASK            = GENMASK(15, 14),
-	GPIO1C7_GPIO            = 0,
-	GPIO1C7_EMMC_DATA5      = (2 << 14),
-
-	GPIO1C6_MASK            = GENMASK(13, 12),
-	GPIO1C6_GPIO            = 0,
-	GPIO1C6_EMMC_DATA4      = (2 << 12),
-
-	GPIO1C5_MASK            = GENMASK(11, 10),
-	GPIO1C5_GPIO            = 0,
-	GPIO1C5_EMMC_DATA3      = (2 << 10),
-
-	GPIO1C4_MASK            = GENMASK(9, 8),
-	GPIO1C4_GPIO            = 0,
-	GPIO1C4_EMMC_DATA2      = (2 << 8),
-
-	GPIO1C3_MASK            = GENMASK(7, 6),
-	GPIO1C3_GPIO            = 0,
-	GPIO1C3_EMMC_DATA1      = (2 << 6),
-
-	GPIO1C2_MASK            = GENMASK(5, 4),
-	GPIO1C2_GPIO            = 0,
-	GPIO1C2_EMMC_DATA0      = (2 << 4),
-};
-
-/* GRF_GPIO1D_IOMUX*/
-enum {
-	GPIO1D3_MASK            = GENMASK(7, 6),
-	GPIO1D3_GPIO            = 0,
-	GPIO1D3_EMMC_PWREN      = (2 << 6),
-
-	GPIO1D2_MASK            = GENMASK(5, 4),
-	GPIO1D2_GPIO            = 0,
-	GPIO1D2_EMMC_CMD        = (2 << 4),
-
-	GPIO1D1_MASK            = GENMASK(3, 2),
-	GPIO1D1_GPIO            = 0,
-	GPIO1D1_EMMC_DATA7      = (2 << 2),
-
-	GPIO1D0_MASK            = GENMASK(1, 0),
-	GPIO1D0_GPIO            = 0,
-	GPIO1D0_EMMC_DATA6      = (2 << 0),
-};
-
-
-/*GRF_GPIO3B_IOMUX*/
-enum {
-	GPIO3B7_MASK            = GENMASK(15, 14),
-	GPIO3B7_GPIO            = 0,
-	GPIO3B7_MAC_RXD0        = (1 << 14),
-
-	GPIO3B6_MASK            = GENMASK(13, 12),
-	GPIO3B6_GPIO            = 0,
-	GPIO3B6_MAC_TXD3        = (1 << 12),
-
-	GPIO3B5_MASK            = GENMASK(11, 10),
-	GPIO3B5_GPIO            = 0,
-	GPIO3B5_MAC_TXEN        = (1 << 10),
-
-	GPIO3B4_MASK            = GENMASK(9, 8),
-	GPIO3B4_GPIO            = 0,
-	GPIO3B4_MAC_COL         = (1 << 8),
-
-	GPIO3B3_MASK            = GENMASK(7, 6),
-	GPIO3B3_GPIO            = 0,
-	GPIO3B3_MAC_CRS         = (1 << 6),
-
-	GPIO3B2_MASK            = GENMASK(5, 4),
-	GPIO3B2_GPIO            = 0,
-	GPIO3B2_MAC_TXD2        = (1 << 4),
-
-	GPIO3B1_MASK            = GENMASK(3, 2),
-	GPIO3B1_GPIO            = 0,
-	GPIO3B1_MAC_TXD1        = (1 << 2),
-
-	GPIO3B0_MASK            = GENMASK(1, 0),
-	GPIO3B0_GPIO            = 0,
-	GPIO3B0_MAC_TXD0        = (1 << 0),
-	GPIO3B0_PWM0            = (2 << 0),
-};
-
-/*GRF_GPIO3C_IOMUX*/
-enum {
-	GPIO3C6_MASK            = GENMASK(13, 12),
-	GPIO3C6_GPIO            = 0,
-	GPIO3C6_MAC_CLK         = (1 << 12),
-
-	GPIO3C5_MASK            = GENMASK(11, 10),
-	GPIO3C5_GPIO            = 0,
-	GPIO3C5_MAC_RXEN        = (1 << 10),
-
-	GPIO3C4_MASK            = GENMASK(9, 8),
-	GPIO3C4_GPIO            = 0,
-	GPIO3C4_MAC_RXDV        = (1 << 8),
-
-	GPIO3C3_MASK            = GENMASK(7, 6),
-	GPIO3C3_GPIO            = 0,
-	GPIO3C3_MAC_MDC         = (1 << 6),
-
-	GPIO3C2_MASK            = GENMASK(5, 4),
-	GPIO3C2_GPIO            = 0,
-	GPIO3C2_MAC_RXD3        = (1 << 4),
-
-	GPIO3C1_MASK            = GENMASK(3, 2),
-	GPIO3C1_GPIO            = 0,
-	GPIO3C1_MAC_RXD2        = (1 << 2),
-
-	GPIO3C0_MASK            = GENMASK(1, 0),
-	GPIO3C0_GPIO            = 0,
-	GPIO3C0_MAC_RXD1        = (1 << 0),
-};
-
-/*GRF_GPIO3D_IOMUX*/
-enum {
-	GPIO3D4_MASK            = GENMASK(9, 8),
-	GPIO3D4_GPIO            = 0,
-	GPIO3D4_MAC_TXCLK       = (1 << 8),
-
-	GPIO3D1_MASK            = GENMASK(3, 2),
-	GPIO3D1_GPIO            = 0,
-	GPIO3D1_MAC_RXCLK       = (1 << 2),
-
-	GPIO3D0_MASK            = GENMASK(1, 0),
-	GPIO3D0_GPIO            = 0,
-	GPIO3D0_MAC_MDIO        = (1 << 0),
-};
-
-/* GRF_SOC_CON0 */
-enum {
-	NOC_RSP_ERR_STALL = BIT(9),
-	MOBILE_DDR_SEL = BIT(4),
-	DDR0_16BIT_EN = BIT(3),
-	MSCH0_MAINDDR3_DDR3 = BIT(2),
-	MSCH0_MAINPARTIALPOP = BIT(1),
-	UPCTL_C_ACTIVE = BIT(0),
-};
-
 /*GRF_SOC_CON11/12/13*/
 enum {
 	MCU_SRAM_BASE_BIT27_BIT12_SHIFT	= 0,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index cf2f834..67695ab 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -16,6 +16,331 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*GRF_GPIO0C_IOMUX*/
+enum {
+	GPIO0C7_MASK	       = GENMASK(15, 14),
+	GPIO0C7_GPIO	       = 0,
+	GPIO0C7_LCDC_D19        = (1 << 14),
+	GPIO0C7_TRACE_D9        = (2 << 14),
+	GPIO0C7_UART1_RTSN      = (3 << 14),
+
+	GPIO0C6_MASK            = GENMASK(13, 12),
+	GPIO0C6_GPIO            = 0,
+	GPIO0C6_LCDC_D18        = (1 << 12),
+	GPIO0C6_TRACE_D8        = (2 << 12),
+	GPIO0C6_UART1_CTSN      = (3 << 12),
+
+	GPIO0C5_MASK            = GENMASK(11, 10),
+	GPIO0C5_GPIO            = 0,
+	GPIO0C5_LCDC_D17        = (1 << 10),
+	GPIO0C5_TRACE_D7        = (2 << 10),
+	GPIO0C5_UART1_SOUT      = (3 << 10),
+
+	GPIO0C4_MASK            = GENMASK(9, 8),
+	GPIO0C4_GPIO            = 0,
+	GPIO0C4_LCDC_D16        = (1 << 8),
+	GPIO0C4_TRACE_D6        = (2 << 8),
+	GPIO0C4_UART1_SIN       = (3 << 8),
+
+	GPIO0C3_MASK            = GENMASK(7, 6),
+	GPIO0C3_GPIO            = 0,
+	GPIO0C3_LCDC_D15        = (1 << 6),
+	GPIO0C3_TRACE_D5        = (2 << 6),
+	GPIO0C3_MCU_JTAG_TDO    = (3 << 6),
+
+	GPIO0C2_MASK            = GENMASK(5, 4),
+	GPIO0C2_GPIO            = 0,
+	GPIO0C2_LCDC_D14        = (1 << 4),
+	GPIO0C2_TRACE_D4        = (2 << 4),
+	GPIO0C2_MCU_JTAG_TDI    = (3 << 4),
+
+	GPIO0C1_MASK            = GENMASK(3, 2),
+	GPIO0C1_GPIO            = 0,
+	GPIO0C1_LCDC_D13        = (1 << 2),
+	GPIO0C1_TRACE_D3        = (2 << 2),
+	GPIO0C1_MCU_JTAG_TRTSN  = (3 << 2),
+
+	GPIO0C0_MASK            = GENMASK(1, 0),
+	GPIO0C0_GPIO            = 0,
+	GPIO0C0_LCDC_D12        = (1 << 0),
+	GPIO0C0_TRACE_D2        = (2 << 0),
+	GPIO0C0_MCU_JTAG_TDO    = (3 << 0),
+};
+
+/*GRF_GPIO0D_IOMUX*/
+enum {
+	GPIO0D7_MASK            = GENMASK(15, 14),
+	GPIO0D7_GPIO            = 0,
+	GPIO0D7_LCDC_DCLK       = (1 << 14),
+	GPIO0D7_TRACE_CTL       = (2 << 14),
+	GPIO0D7_PMU_DEBUG5      = (3 << 14),
+
+	GPIO0D6_MASK            = GENMASK(13, 12),
+	GPIO0D6_GPIO            = 0,
+	GPIO0D6_LCDC_DEN        = (1 << 12),
+	GPIO0D6_TRACE_CLK       = (2 << 12),
+	GPIO0D6_PMU_DEBUG4      = (3 << 12),
+
+	GPIO0D5_MASK            = GENMASK(11, 10),
+	GPIO0D5_GPIO            = 0,
+	GPIO0D5_LCDC_VSYNC             = (1 << 10),
+	GPIO0D5_TRACE_D15       = (2 << 10),
+	GPIO0D5_PMU_DEBUG3      = (3 << 10),
+
+	GPIO0D4_MASK            = GENMASK(9, 8),
+	GPIO0D4_GPIO            = 0,
+	GPIO0D4_LCDC_HSYNC      = (1 << 8),
+	GPIO0D4_TRACE_D14       = (2 << 8),
+	GPIO0D4_PMU_DEBUG2      = (3 << 8),
+
+	GPIO0D3_MASK            = GENMASK(7, 6),
+	GPIO0D3_GPIO            = 0,
+	GPIO0D3_LCDC_D23        = (1 << 6),
+	GPIO0D3_TRACE_D13       = (2 << 6),
+	GPIO0D3_UART4_SIN       = (3 << 6),
+
+	GPIO0D2_MASK            = GENMASK(5, 4),
+	GPIO0D2_GPIO            = 0,
+	GPIO0D2_LCDC_D22        = (1 << 4),
+	GPIO0D2_TRACE_D12       = (2 << 4),
+	GPIO0D2_UART4_SOUT      = (3 << 4),
+
+	GPIO0D1_MASK            = GENMASK(3, 2),
+	GPIO0D1_GPIO            = 0,
+	GPIO0D1_LCDC_D21        = (1 << 2),
+	GPIO0D1_TRACE_D11       = (2 << 2),
+	GPIO0D1_UART4_RTSN      = (3 << 2),
+
+	GPIO0D0_MASK            = GENMASK(1, 0),
+	GPIO0D0_GPIO            = 0,
+	GPIO0D0_LCDC_D20        = (1 << 0),
+	GPIO0D0_TRACE_D10       = (2 << 0),
+	GPIO0D0_UART4_CTSN      = (3 << 0),
+};
+
+/*GRF_GPIO2A_IOMUX*/
+enum {
+	GPIO2A7_MASK            = GENMASK(15, 14),
+	GPIO2A7_GPIO            = 0,
+	GPIO2A7_SDMMC0_D2       = (1 << 14),
+	GPIO2A7_JTAG_TCK        = (2 << 14),
+
+	GPIO2A6_MASK            = GENMASK(13, 12),
+	GPIO2A6_GPIO            = 0,
+	GPIO2A6_SDMMC0_D1       = (1 << 12),
+	GPIO2A6_UART2_SIN       = (2 << 12),
+
+	GPIO2A5_MASK            = GENMASK(11, 10),
+	GPIO2A5_GPIO            = 0,
+	GPIO2A5_SDMMC0_D0       = (1 << 10),
+	GPIO2A5_UART2_SOUT      = (2 << 10),
+
+	GPIO2A4_MASK            = GENMASK(9, 8),
+	GPIO2A4_GPIO     = 0,
+	GPIO2A4_FLASH_DQS       = (1 << 8),
+	GPIO2A4_EMMC_CLKOUT     = (2 << 8),
+
+	GPIO2A3_MASK            = GENMASK(7, 6),
+	GPIO2A3_GPIO            = 0,
+	GPIO2A3_FLASH_CSN3      = (1 << 6),
+	GPIO2A3_EMMC_RSTNOUT    = (2 << 6),
+
+	GPIO2A2_MASK            = GENMASK(5, 4),
+	GPIO2A2_GPIO            = 0,
+	GPIO2A2_FLASH_CSN2      = (1 << 4),
+
+	GPIO2A1_MASK            = GENMASK(3, 2),
+	GPIO2A1_GPIO            = 0,
+	GPIO2A1_FLASH_CSN1      = (1 << 2),
+
+	GPIO2A0_MASK            = GENMASK(1, 0),
+	GPIO2A0_GPIO            = 0,
+	GPIO2A0_FLASH_CSN0      = (1 << 0),
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+	GPIO2D7_MASK            = GENMASK(15, 14),
+	GPIO2D7_GPIO            = 0,
+	GPIO2D7_SDIO0_D3        = (1 << 14),
+
+	GPIO2D6_MASK            = GENMASK(13, 12),
+	GPIO2D6_GPIO            = 0,
+	GPIO2D6_SDIO0_D2        = (1 << 12),
+
+	GPIO2D5_MASK            = GENMASK(11, 10),
+	GPIO2D5_GPIO            = 0,
+	GPIO2D5_SDIO0_D1        = (1 << 10),
+
+	GPIO2D4_MASK            = GENMASK(9, 8),
+	GPIO2D4_GPIO            = 0,
+	GPIO2D4_SDIO0_D0        = (1 << 8),
+
+	GPIO2D3_MASK            = GENMASK(7, 6),
+	GPIO2D3_GPIO            = 0,
+	GPIO2D3_UART0_RTS0      = (1 << 6),
+
+	GPIO2D2_MASK            = GENMASK(5, 4),
+	GPIO2D2_GPIO            = 0,
+	GPIO2D2_UART0_CTS0      = (1 << 4),
+
+	GPIO2D1_MASK            = GENMASK(3, 2),
+	GPIO2D1_GPIO            = 0,
+	GPIO2D1_UART0_SOUT      = (1 << 2),
+
+	GPIO2D0_MASK            = GENMASK(1, 0),
+	GPIO2D0_GPIO            = 0,
+	GPIO2D0_UART0_SIN       = (1 << 0),
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+	GPIO1B7_MASK            = GENMASK(15, 14),
+	GPIO1B7_GPIO            = 0,
+	GPIO1B7_SPI1_CSN0       = (2 << 14),
+
+	GPIO1B6_MASK            = GENMASK(13, 12),
+	GPIO1B6_GPIO            = 0,
+	GPIO1B6_SPI1_CLK        = (2 << 12),
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+	GPIO1C7_MASK            = GENMASK(15, 14),
+	GPIO1C7_GPIO            = 0,
+	GPIO1C7_EMMC_DATA5      = (2 << 14),
+
+	GPIO1C6_MASK            = GENMASK(13, 12),
+	GPIO1C6_GPIO            = 0,
+	GPIO1C6_EMMC_DATA4      = (2 << 12),
+
+	GPIO1C5_MASK            = GENMASK(11, 10),
+	GPIO1C5_GPIO            = 0,
+	GPIO1C5_EMMC_DATA3      = (2 << 10),
+
+	GPIO1C4_MASK            = GENMASK(9, 8),
+	GPIO1C4_GPIO            = 0,
+	GPIO1C4_EMMC_DATA2      = (2 << 8),
+
+	GPIO1C3_MASK            = GENMASK(7, 6),
+	GPIO1C3_GPIO            = 0,
+	GPIO1C3_EMMC_DATA1      = (2 << 6),
+
+	GPIO1C2_MASK            = GENMASK(5, 4),
+	GPIO1C2_GPIO            = 0,
+	GPIO1C2_EMMC_DATA0      = (2 << 4),
+
+	GPIO1C1_MASK            = GENMASK(3, 2),
+	GPIO1C1_GPIO            = 0,
+	GPIO1C1_SPI1_RXD        = (2 << 2),
+
+	GPIO1C0_MASK            = GENMASK(1, 0),
+	GPIO1C0_GPIO            = 0,
+	GPIO1C0_SPI1_TXD        = (2 << 0),
+};
+
+/* GRF_GPIO1D_IOMUX*/
+enum {
+	GPIO1D3_MASK            = GENMASK(7, 6),
+	GPIO1D3_GPIO            = 0,
+	GPIO1D3_EMMC_PWREN      = (2 << 6),
+
+	GPIO1D2_MASK            = GENMASK(5, 4),
+	GPIO1D2_GPIO            = 0,
+	GPIO1D2_EMMC_CMD        = (2 << 4),
+
+	GPIO1D1_MASK            = GENMASK(3, 2),
+	GPIO1D1_GPIO            = 0,
+	GPIO1D1_EMMC_DATA7      = (2 << 2),
+
+	GPIO1D0_MASK            = GENMASK(1, 0),
+	GPIO1D0_GPIO            = 0,
+	GPIO1D0_EMMC_DATA6      = (2 << 0),
+};
+
+
+/*GRF_GPIO3B_IOMUX*/
+enum {
+	GPIO3B7_MASK            = GENMASK(15, 14),
+	GPIO3B7_GPIO            = 0,
+	GPIO3B7_MAC_RXD0        = (1 << 14),
+
+	GPIO3B6_MASK            = GENMASK(13, 12),
+	GPIO3B6_GPIO            = 0,
+	GPIO3B6_MAC_TXD3        = (1 << 12),
+
+	GPIO3B5_MASK            = GENMASK(11, 10),
+	GPIO3B5_GPIO            = 0,
+	GPIO3B5_MAC_TXEN        = (1 << 10),
+
+	GPIO3B4_MASK            = GENMASK(9, 8),
+	GPIO3B4_GPIO            = 0,
+	GPIO3B4_MAC_COL         = (1 << 8),
+
+	GPIO3B3_MASK            = GENMASK(7, 6),
+	GPIO3B3_GPIO            = 0,
+	GPIO3B3_MAC_CRS         = (1 << 6),
+
+	GPIO3B2_MASK            = GENMASK(5, 4),
+	GPIO3B2_GPIO            = 0,
+	GPIO3B2_MAC_TXD2        = (1 << 4),
+
+	GPIO3B1_MASK            = GENMASK(3, 2),
+	GPIO3B1_GPIO            = 0,
+	GPIO3B1_MAC_TXD1        = (1 << 2),
+
+	GPIO3B0_MASK            = GENMASK(1, 0),
+	GPIO3B0_GPIO            = 0,
+	GPIO3B0_MAC_TXD0        = (1 << 0),
+	GPIO3B0_PWM0            = (2 << 0),
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+	GPIO3C6_MASK            = GENMASK(13, 12),
+	GPIO3C6_GPIO            = 0,
+	GPIO3C6_MAC_CLK         = (1 << 12),
+
+	GPIO3C5_MASK            = GENMASK(11, 10),
+	GPIO3C5_GPIO            = 0,
+	GPIO3C5_MAC_RXEN        = (1 << 10),
+
+	GPIO3C4_MASK            = GENMASK(9, 8),
+	GPIO3C4_GPIO            = 0,
+	GPIO3C4_MAC_RXDV        = (1 << 8),
+
+	GPIO3C3_MASK            = GENMASK(7, 6),
+	GPIO3C3_GPIO            = 0,
+	GPIO3C3_MAC_MDC         = (1 << 6),
+
+	GPIO3C2_MASK            = GENMASK(5, 4),
+	GPIO3C2_GPIO            = 0,
+	GPIO3C2_MAC_RXD3        = (1 << 4),
+
+	GPIO3C1_MASK            = GENMASK(3, 2),
+	GPIO3C1_GPIO            = 0,
+	GPIO3C1_MAC_RXD2        = (1 << 2),
+
+	GPIO3C0_MASK            = GENMASK(1, 0),
+	GPIO3C0_GPIO            = 0,
+	GPIO3C0_MAC_RXD1        = (1 << 0),
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+	GPIO3D4_MASK            = GENMASK(9, 8),
+	GPIO3D4_GPIO            = 0,
+	GPIO3D4_MAC_TXCLK       = (1 << 8),
+
+	GPIO3D1_MASK            = GENMASK(3, 2),
+	GPIO3D1_GPIO            = 0,
+	GPIO3D1_MAC_RXCLK       = (1 << 2),
+
+	GPIO3D0_MASK            = GENMASK(1, 0),
+	GPIO3D0_GPIO            = 0,
+	GPIO3D0_MAC_MDIO        = (1 << 0),
+};
+
 struct rk3368_pinctrl_priv {
 	struct rk3368_grf *grf;
 	struct rk3368_pmu_grf *pmugrf;