Patchwork [U-Boot,v3] ppc4xx: Add DLVision-10G board support

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Submitter Dirk Eibach
Date Jan. 19, 2011, 12:37 p.m.
Message ID <1295440671-20653-1-git-send-email-eibach@gdsys.de>
Download mbox | patch
Permalink /patch/79460/
State Superseded
Headers show

Comments

Dirk Eibach - Jan. 19, 2011, 12:37 p.m.
Board support for the Guntermann & Drunck DLVision-10G.
Adds support for multiple FPGAs per board for gdsys 405ep
architecture.
Adds support for dual link osd hardware for gdsys 405ep.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
---
Replaces
	- 0001-ppc4xx-Add-DLVision-10G-board-support.patch
	- 0002-ppc4xx-Support-multiple-FPGAs.patch
	- 0003-ppc4xx-Support-dual-link-OSD.patch

Changes for v2:
	- define EBC register values through appropriate macros
	- fix condition for extension of struct	global_data

Changes for v3:
	- added missing commits from v2

Conversion to struct based register access will follow in a sperate patch.

 MAINTAINERS                            |    1 +
 arch/powerpc/include/asm/global_data.h |    3 +
 board/gdsys/405ep/405ep.c              |   64 +++++--
 board/gdsys/405ep/Makefile             |    1 +
 board/gdsys/405ep/dlvision-10g.c       |  243 ++++++++++++++++++++++++
 board/gdsys/405ep/io.c                 |    8 +-
 board/gdsys/405ep/iocon.c              |   14 +-
 board/gdsys/common/Makefile            |    1 +
 board/gdsys/common/fpga.h              |   16 ++-
 board/gdsys/common/osd.c               |  303 +++++++++++++++++++++++--------
 board/gdsys/common/osd.h               |    2 +-
 boards.cfg                             |    1 +
 include/configs/dlvision-10g.h         |  322 ++++++++++++++++++++++++++++++++
 include/configs/io.h                   |    7 +-
 include/configs/iocon.h                |   27 +++-
 15 files changed, 907 insertions(+), 106 deletions(-)
 create mode 100644 board/gdsys/405ep/dlvision-10g.c
 create mode 100644 include/configs/dlvision-10g.h
Wolfgang Denk - Jan. 19, 2011, 1:45 p.m.
Dear Dirk Eibach,

In message <1295440671-20653-1-git-send-email-eibach@gdsys.de> you wrote:
> Board support for the Guntermann & Drunck DLVision-10G.
> Adds support for multiple FPGAs per board for gdsys 405ep
> architecture.
> Adds support for dual link osd hardware for gdsys 405ep.
> 
> Signed-off-by: Dirk Eibach <eibach@gdsys.de>
> ---
> Replaces
> 	- 0001-ppc4xx-Add-DLVision-10G-board-support.patch
> 	- 0002-ppc4xx-Support-multiple-FPGAs.patch
> 	- 0003-ppc4xx-Support-dual-link-OSD.patch
> 
> Changes for v2:
> 	- define EBC register values through appropriate macros
> 	- fix condition for extension of struct	global_data
> 
> Changes for v3:
> 	- added missing commits from v2
> 
> Conversion to struct based register access will follow in a sperate patch.

What does that mean? We need a single patch that includes everything
at once.


Best regards,

Wolfgang Denk

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 0590ad9..ea882c8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -142,6 +142,7 @@  Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
 	dlvision        PPC405EP
+	dlvision-10g	PPC405EP
 	gdppc440etx	PPC440EP/GR
 	intip		PPC460EX
 	io		PPC405EP
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 2e218de..a33ca2f 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -172,6 +172,9 @@  typedef	struct	global_data {
 #if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
 	unsigned long kbd_status;
 #endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+	unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
+#endif
 #if defined(CONFIG_WD_MAX_RATE)
 	unsigned long long wdt_last;	/* trace watch-dog triggering rate */
 #endif
diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index d3bd233..84ea573 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -26,6 +26,7 @@ 
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
 
 #include "../common/fpga.h"
 
@@ -36,8 +37,29 @@ 
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+	return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+	if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+		puts("       Waiting for FPGA-DONE timed out.\n");
+	if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+		puts("       FPGA reflection test failed.\n");
+}
+
 int board_early_init_f(void)
 {
+	unsigned k;
+	unsigned ctr;
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		gd->fpga_state[k] = 0;
+
 	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
 	mtdcr(UIC0CR, 0x00000000);	/* set all to be non-critical */
@@ -66,10 +88,18 @@  int board_early_init_f(void)
 
 	/*
 	 * wait for fpga-done
-	 * fail ungraceful if fpga is not configuring properly
 	 */
-	while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
-		;
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		ctr = 0;
+		while (!(in_le16((void *)LATCH2_BASE)
+			& CONFIG_SYS_FPGA_DONE(k))) {
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+				break;
+			}
+		}
+	}
 
 	/*
 	 * setup io-latches for boot (stop reset)
@@ -78,15 +108,25 @@  int board_early_init_f(void)
 	out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 	out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 
-	/*
-	 * wait for fpga out of reset
-	 * fail ungraceful if fpga is not working properly
-	 */
-	while (1) {
-		fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
-		if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
-			REFLECTION_TESTPATTERN_INV)
-			break;
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+		/*
+		 * wait for fpga out of reset
+		 * fail ungraceful if fpga is not working properly
+		 */
+		ctr = 0;
+		while (1) {
+			fpga_set_reg(k, CONFIG_SYS_FPGA_RFL_LOW,
+				REFLECTION_TESTPATTERN);
+			if (fpga_get_reg(k, CONFIG_SYS_FPGA_RFL_HIGH) ==
+				REFLECTION_TESTPATTERN_INV)
+				break;
+			udelay(100000);
+			if (ctr++ > 5) {
+				gd->fpga_state[k] |=
+					FPGA_STATE_REFLECTION_FAILED;
+				break;
+			}
+		}
 	}
 
 	return 0;
diff --git a/board/gdsys/405ep/Makefile b/board/gdsys/405ep/Makefile
index ed31207..169418c 100644
--- a/board/gdsys/405ep/Makefile
+++ b/board/gdsys/405ep/Makefile
@@ -27,6 +27,7 @@  LIB	= $(obj)lib$(BOARD).o
 
 COBJS-$(CONFIG_IO) += io.o
 COBJS-$(CONFIG_IOCON) += iocon.o
+COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
 
 COBJS   := $(BOARD).o $(COBJS-y)
 SOBJS   =
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
new file mode 100644
index 0000000..740cceb
--- /dev/null
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -0,0 +1,243 @@ 
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include "../common/fpga.h"
+#include "../common/osd.h"
+
+enum {
+	REG_VERSIONS = 0x0002,
+	REG_FPGA_VERSION = 0x0004,
+	REG_FPGA_FEATURES = 0x0006,
+};
+
+enum {
+	UNITTYPE_VIDEO_USER = 0,
+	UNITTYPE_MAIN_USER = 1,
+	UNITTYPE_VIDEO_SERVER = 2,
+	UNITTYPE_MAIN_SERVER = 3,
+};
+
+enum {
+	HWVER_101 = 0,
+	HWVER_110 = 1,
+};
+
+enum {
+	AUDIO_NONE = 0,
+	AUDIO_TX = 1,
+	AUDIO_RX = 2,
+	AUDIO_RXTX = 3,
+};
+
+enum {
+	SYSCLK_156250 = 2,
+};
+
+enum {
+	RAM_NONE = 0,
+	RAM_DDR2_32 = 1,
+	RAM_DDR2_64 = 2,
+};
+
+static void print_fpga_info(unsigned dev)
+{
+	u16 versions = fpga_get_reg(dev, REG_VERSIONS);
+	u16 fpga_version = fpga_get_reg(dev, REG_FPGA_VERSION);
+	u16 fpga_features = fpga_get_reg(dev, REG_FPGA_FEATURES);
+	unsigned unit_type;
+	unsigned hardware_version;
+	unsigned feature_compression;
+	unsigned feature_rs232;
+	unsigned feature_audio;
+	unsigned feature_sysclock;
+	unsigned feature_ramconfig;
+	unsigned feature_carrier_speed;
+	unsigned feature_carriers;
+	unsigned feature_video_channels;
+	int fpga_state = get_fpga_state(dev);
+
+	printf("FPGA%d: ", dev);
+
+	hardware_version = versions & 0x000f;
+
+	if (fpga_state
+	    && !((hardware_version == HWVER_101)
+		 && (fpga_state == FPGA_STATE_DONE_FAILED))) {
+		puts("not available\n");
+		print_fpga_state(dev);
+		return;
+	}
+
+	unit_type = (versions >> 4) & 0x000f;
+	hardware_version = versions & 0x000f;
+	feature_compression = (fpga_features >> 13) & 0x0003;
+	feature_rs232 = fpga_features & (1<<11);
+	feature_audio = (fpga_features >> 9) & 0x0003;
+	feature_sysclock = (fpga_features >> 7) & 0x0003;
+	feature_ramconfig = (fpga_features >> 5) & 0x0003;
+	feature_carrier_speed = fpga_features & (1<<4);
+	feature_carriers = (fpga_features >> 2) & 0x0003;
+	feature_video_channels = fpga_features & 0x0003;
+
+	switch (unit_type) {
+	case UNITTYPE_VIDEO_USER:
+		printf("Videochannel Userside");
+		break;
+
+	case UNITTYPE_MAIN_USER:
+		printf("Mainchannel Userside");
+		break;
+
+	case UNITTYPE_VIDEO_SERVER:
+		printf("Videochannel Serverside");
+		break;
+
+	case UNITTYPE_MAIN_SERVER:
+		printf("Mainchannel Serverside");
+		break;
+
+	default:
+		printf("UnitType %d(not supported)", unit_type);
+		break;
+	}
+
+	switch (hardware_version) {
+	case HWVER_101:
+		printf(" HW-Ver 1.01\n");
+		break;
+
+	case HWVER_110:
+		printf(" HW-Ver 1.10\n");
+		break;
+
+	default:
+		printf(" HW-Ver %d(not supported)\n",
+		       hardware_version);
+		break;
+	}
+
+	printf("       FPGA V %d.%02d, features:",
+		fpga_version / 100, fpga_version % 100);
+
+	printf(" %sRS232", feature_rs232 ? "" : "no ");
+
+	switch (feature_audio) {
+	case AUDIO_NONE:
+		printf(", no audio");
+		break;
+
+	case AUDIO_TX:
+		printf(", audio tx");
+		break;
+
+	case AUDIO_RX:
+		printf(", audio rx");
+		break;
+
+	case AUDIO_RXTX:
+		printf(", audio rx+tx");
+		break;
+
+	default:
+		printf(", audio %d(not supported)", feature_audio);
+		break;
+	}
+
+	switch (feature_sysclock) {
+	case SYSCLK_156250:
+		printf(", clock 156.25 MHz");
+		break;
+
+	default:
+		printf(", clock %d(not supported)", feature_sysclock);
+		break;
+	}
+
+	puts(",\n       ");
+
+	switch (feature_ramconfig) {
+	case RAM_NONE:
+		printf("no RAM");
+		break;
+
+	case RAM_DDR2_32:
+		printf("RAM 32 bit DDR2");
+		break;
+
+	case RAM_DDR2_64:
+		printf("RAM 64 bit DDR2");
+		break;
+
+	default:
+		printf("RAM %d(not supported)", feature_ramconfig);
+		break;
+	}
+
+	printf(", %d carrier(s) %s", feature_carriers,
+		feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
+
+	printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+	unsigned k;
+	char *s = getenv("serial#");
+
+	printf("Board: ");
+
+	printf("DLVision 10G");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+
+	puts("\n");
+
+	for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+		print_fpga_info(k);
+
+	return 0;
+}
+
+int last_stage_init(void)
+{
+	unsigned k;
+
+	for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
+		if (!get_fpga_state(k)
+		    || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
+			osd_probe(k);
+
+	return 0;
+}
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 80877b6..b2c02bf 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -95,9 +95,9 @@  err_out:
 int checkboard(void)
 {
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	u16 versions = fpga_get_reg(0, REG_VERSIONS);
+	u16 fpga_version = fpga_get_reg(0, REG_FPGA_VERSION);
+	u16 fpga_features = fpga_get_reg(0, REG_FPGA_FEATURES);
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_channels;
@@ -175,7 +175,7 @@  int last_stage_init(void)
 		configure_gbit_phy(k);
 
 	/* take fpga serdes blocks out of reset */
-	fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+	fpga_set_reg(0, REG_QUAD_SERDES_RESET, 0);
 
 	return 0;
 }
diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index ecd6cb2..d5196c1 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -75,9 +75,9 @@  enum {
 int checkboard(void)
 {
 	char *s = getenv("serial#");
-	u16 versions = fpga_get_reg(REG_VERSIONS);
-	u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
-	u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+	u16 versions = fpga_get_reg(0, REG_VERSIONS);
+	u16 fpga_version = fpga_get_reg(0, REG_FPGA_VERSION);
+	u16 fpga_features = fpga_get_reg(0, REG_FPGA_FEATURES);
 	unsigned unit_type;
 	unsigned hardware_version;
 	unsigned feature_compression;
@@ -214,7 +214,7 @@  int checkboard(void)
 
 int last_stage_init(void)
 {
-	return osd_probe();
+	return osd_probe(0);
 }
 
 /*
@@ -222,15 +222,15 @@  int last_stage_init(void)
  */
 void fpga_gpio_set(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
 }
 
 void fpga_gpio_clear(int pin)
 {
-	out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+	out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
 }
 
 int fpga_gpio_get(int pin)
 {
-	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+	return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
 }
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index 2257037..4c7fc99 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -31,6 +31,7 @@  LIB	= $(obj)lib$(VENDOR).o
 
 COBJS-$(CONFIG_IO) += miiphybb.o
 COBJS-$(CONFIG_IOCON) += osd.o
+COBJS-$(CONFIG_DLVISION_10G) += osd.o
 
 COBJS   := $(COBJS-y)
 SOBJS   =
diff --git a/board/gdsys/common/fpga.h b/board/gdsys/common/fpga.h
index c1434e7..29846b7 100644
--- a/board/gdsys/common/fpga.h
+++ b/board/gdsys/common/fpga.h
@@ -24,14 +24,22 @@ 
 #ifndef _FPGA_H_
 #define _FPGA_H_
 
-static inline u16 fpga_get_reg(unsigned reg)
+enum {
+	FPGA_STATE_DONE_FAILED = 1 << 0,
+	FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+};
+
+int get_fpga_state(unsigned dev);
+void print_fpga_state(unsigned dev);
+
+static inline u16 fpga_get_reg(unsigned dev, unsigned reg)
 {
-	return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
+	return in_le16((void *)(CONFIG_SYS_FPGA_BASE(dev) + reg));
 }
 
-static inline void fpga_set_reg(unsigned reg, u16 val)
+static inline void fpga_set_reg(unsigned dev, unsigned reg, u16 val)
 {
-	return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
+	return out_le16((void *)(CONFIG_SYS_FPGA_BASE(dev) + reg), val);
 }
 
 #endif
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 239c870..9968dbf 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -29,6 +29,12 @@ 
 
 #define CH7301_I2C_ADDR 0x75
 
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
 #define PIXCLK_640_480_60 25180000
 
 #define BASE_WIDTH 32
@@ -38,12 +44,18 @@ 
 enum {
 	REG_CONTROL = 0x0010,
 	REG_MPC3W_CONTROL = 0x001a,
+	REG_EXT_INTERRUPT = 0x001c,
+	REG_EXT_INTERRUPT_ENABLE = 0x001e,
+	REG_IIC_WRITE_MAILBOX = 0x0030,
+	REG_IIC_WRITE_MAILBOX_EXT = 0x0032,
+	REG_IIC_READ_MAILBOX = 0x0034,
+	REG_IIC_READ_MAILBOX_EXT = 0x0036,
 	REG_VIDEOCONTROL = 0x0042,
-	REG_OSDVERSION = 0x0100,
-	REG_OSDFEATURES = 0x0102,
-	REG_OSDCONTROL = 0x0104,
-	REG_XY_SIZE = 0x0106,
-	REG_VIDEOMEM = 0x0800,
+	REG_OSDVERSION = CONFIG_SYS_FPGA_OSD_BASE + 0x0000,
+	REG_OSDFEATURES = CONFIG_SYS_FPGA_OSD_BASE + 0x0002,
+	REG_OSDCONTROL = CONFIG_SYS_FPGA_OSD_BASE + 0x0004,
+	REG_XY_SIZE = CONFIG_SYS_FPGA_OSD_BASE + 0x0006,
+	REG_VIDEOMEM = CONFIG_SYS_FPGA_OSD_MEM,
 };
 
 enum {
@@ -67,6 +79,37 @@  enum {
 	CH7301_DSP = 0x56,		/* DVI Sync polarity Register */
 };
 
+#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
+static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
+{
+	while (fpga_get_reg(screen, REG_EXT_INTERRUPT) & (1 << 12))
+		;
+	fpga_set_reg(screen, REG_IIC_WRITE_MAILBOX_EXT,
+		reg | (data << 8));
+	fpga_set_reg(screen, REG_IIC_WRITE_MAILBOX,
+		0xc400 | (slave << 1));
+}
+
+static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
+{
+	unsigned int ctr = 0;
+	while (fpga_get_reg(screen, REG_EXT_INTERRUPT) & (1 << 12))
+		;
+	fpga_set_reg(screen, REG_EXT_INTERRUPT, 1 << 14);
+	fpga_set_reg(screen, REG_IIC_WRITE_MAILBOX_EXT, reg);
+	fpga_set_reg(screen, REG_IIC_WRITE_MAILBOX, 0xc000 | (slave << 1));
+	while (!(fpga_get_reg(screen, REG_EXT_INTERRUPT) & (1 << 14))) {
+		udelay(100000);
+		if (ctr++ > 5) {
+			printf("iic receive timeout\n");
+			break;
+		}
+	}
+	return fpga_get_reg(screen, REG_IIC_READ_MAILBOX_EXT) >> 8;
+}
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
 static void mpc92469ac_calc_parameters(unsigned int fout,
 	unsigned int *post_div, unsigned int *feedback_div)
 {
@@ -92,7 +135,7 @@  static void mpc92469ac_calc_parameters(unsigned int fout,
 	*feedback_div = m;
 }
 
-static void mpc92469ac_set(unsigned int fout)
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
 {
 	unsigned int n;
 	unsigned int m;
@@ -114,17 +157,83 @@  static void mpc92469ac_set(unsigned int fout)
 		break;
 	}
 
-	fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
+	fpga_set_reg(screen, REG_MPC3W_CONTROL, (bitval << 9) | m);
 }
+#endif
 
-static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
+#ifdef CONFIG_SYS_ICS8N3QV01
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+	unsigned int *_mint, unsigned int *_mfrac,
+	unsigned int *_n)
+{
+	unsigned int n;
+	unsigned int foutiic;
+	unsigned int fvcoiic;
+	unsigned int mint;
+	unsigned long long mfrac;
+
+	n = 2550000000U / fout;
+	if ((n & 1) && (n > 5))
+		n -= 1;
+
+	foutiic = fout - (fout / 10000);
+	fvcoiic = foutiic * n;
+
+	mint = fvcoiic / 114285000;
+	if ((mint < 17) || (mint > 63))
+		printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+	mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+		/ 114285000LL;
+
+	*_mint = mint;
+	*_mfrac = mfrac;
+	*_n = n;
+}
+
+static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+{
+	unsigned int n;
+	unsigned int mint;
+	unsigned int mfrac;
+	u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+	ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n);
+
+	reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+	reg0 |= (mint & 0x1f) << 1;
+	reg0 |= (mfrac >> 17) & 0x01;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+	reg4 = mfrac >> 9;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+	reg8 = mfrac >> 1;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+	reg12 = mfrac << 7;
+	reg12 |= n & 0x7f;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+	reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+	reg18 |= 0x20;
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+	reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+	reg20 |= mint & (1 << 5);
+	fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+	u16 *data, size_t charcount)
 {
 	unsigned int k;
 
 	for (k = 0; k < charcount; ++k) {
 		if (offset + k >= BUFSIZE)
 			return -1;
-		fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
+		fpga_set_reg(screen, REG_VIDEOMEM + 2 * (offset + k), data[k]);
 	}
 
 	return charcount;
@@ -132,46 +241,57 @@  static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
 
 static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	unsigned x;
-	unsigned y;
-	unsigned charcount;
-	unsigned len;
-	u8 color;
-	unsigned int k;
-	u16 buf[BUFSIZE];
-	char *text;
-
-	if (argc < 5) {
-		return cmd_usage(cmdtp);
+	unsigned screen;
+
+	for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned charcount;
+		unsigned len;
+		u8 color;
+		unsigned int k;
+		u16 buf[BUFSIZE];
+		char *text;
+		int res;
+
+		if (argc < 5) {
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		color = simple_strtoul(argv[3], NULL, 16);
+		text = argv[4];
+		charcount = strlen(text);
+		len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+
+		for (k = 0; k < len; ++k)
+			buf[k] = (text[k] << 8) | color;
+
+		res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
+		if (res < 0)
+			return res;
 	}
 
-	x = simple_strtoul(argv[1], NULL, 16);
-	y = simple_strtoul(argv[2], NULL, 16);
-	color = simple_strtoul(argv[3], NULL, 16);
-	text = argv[4];
-	charcount = strlen(text);
-	len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
-
-	for (k = 0; k < len; ++k)
-		buf[k] = (text[k] << 8) | color;
-
-	return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
+	return 0;
 }
 
-int osd_probe(void)
+int osd_probe(unsigned screen)
 {
-	u8 value;
-	u16 version = fpga_get_reg(REG_OSDVERSION);
-	u16 features = fpga_get_reg(REG_OSDFEATURES);
+	u16 version = fpga_get_reg(screen, REG_OSDVERSION);
+	u16 features = fpga_get_reg(screen, REG_OSDFEATURES);
 	unsigned width;
 	unsigned height;
+	u8 value;
 
 	width = ((features & 0x3f00) >> 8) + 1;
 	height = (features & 0x001f) + 1;
 
-	printf("OSD:   Digital-OSD version %01d.%02d, %d" "x%d characters\n",
-		version/100, version%100, width, height);
+	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+		screen, version/100, version%100, width, height);
 
+#ifdef CONFIG_SYS_CH7301
 	value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
 	if (value != 0x17) {
 		printf("       Probing CH7301 failed, DID %02x\n", value);
@@ -182,51 +302,86 @@  int osd_probe(void)
 	i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
 	i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
 	i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+#endif
 
-	mpc92469ac_set(PIXCLK_640_480_60);
-	fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
-	fpga_set_reg(REG_OSDCONTROL, 0x0049);
+#ifdef CONFIG_SYS_MPC92469AC
+	mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
 
-	fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
+#ifdef CONFIG_SYS_ICS8N3QV01
+	ics8n3qv01_set(screen, PIXCLK_640_480_60);
+#endif
+
+#ifdef CONFIG_SYS_SIL1178
+	value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+	if (value != 0x06) {
+		printf("       Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
+		return -1;
+	}
+	/* magic initialization sequence adapted from datasheet */
+	fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+	fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+#endif
+
+	fpga_set_reg(screen, REG_VIDEOCONTROL, 0x0002);
+	fpga_set_reg(screen, REG_OSDCONTROL, 0x0049);
+
+	fpga_set_reg(screen, REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
 
 	return 0;
 }
 
 int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	unsigned x;
-	unsigned y;
-	unsigned k;
-	u16 buffer[BASE_WIDTH];
-	char *rp;
-	u16 *wp = buffer;
-	unsigned count = (argc > 4) ?  simple_strtoul(argv[4], NULL, 16) : 1;
-
-	if ((argc < 4) || (strlen(argv[3]) % 4)) {
-		return cmd_usage(cmdtp);
-	}
-
-	x = simple_strtoul(argv[1], NULL, 16);
-	y = simple_strtoul(argv[2], NULL, 16);
-	rp = argv[3];
-
-
-	while (*rp) {
-		char substr[5];
-
-		memcpy(substr, rp, 4);
-		substr[4] = 0;
-		*wp = simple_strtoul(substr, NULL, 16);
-
-		rp += 4;
-		wp++;
-		if (wp - buffer > BASE_WIDTH)
-			break;
-	}
-
-	for (k = 0; k < count; ++k) {
-		unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
-		osd_write_videomem(offset, buffer, wp - buffer);
+	unsigned screen;
+
+	for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+		unsigned x;
+		unsigned y;
+		unsigned k;
+		u16 buffer[BASE_WIDTH];
+		char *rp;
+		u16 *wp = buffer;
+		unsigned count = (argc > 4) ?
+			simple_strtoul(argv[4], NULL, 16) : 1;
+
+		if ((argc < 4) || (strlen(argv[3]) % 4)) {
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		x = simple_strtoul(argv[1], NULL, 16);
+		y = simple_strtoul(argv[2], NULL, 16);
+		rp = argv[3];
+
+
+		while (*rp) {
+			char substr[5];
+
+			memcpy(substr, rp, 4);
+			substr[4] = 0;
+			*wp = simple_strtoul(substr, NULL, 16);
+
+			rp += 4;
+			wp++;
+			if (wp - buffer > BASE_WIDTH)
+				break;
+		}
+
+		for (k = 0; k < count; ++k) {
+			unsigned offset =
+				y * BASE_WIDTH + x + k * (wp - buffer);
+			osd_write_videomem(screen, offset, buffer,
+				wp - buffer);
+		}
 	}
 
 	return 0;
diff --git a/board/gdsys/common/osd.h b/board/gdsys/common/osd.h
index 4431cbc..c59d9c3 100644
--- a/board/gdsys/common/osd.h
+++ b/board/gdsys/common/osd.h
@@ -24,6 +24,6 @@ 
 #ifndef _OSD_H_
 #define _OSD_H_
 
-int osd_probe(void);
+int osd_probe(unsigned screen);
 
 #endif
diff --git a/boards.cfg b/boards.cfg
index dcd5a12..4a40685 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -713,6 +713,7 @@  VOM405                       powerpc     ppc4xx      vom405              esd
 WUH405                       powerpc     ppc4xx      wuh405              esd
 devconcenter                 powerpc     ppc4xx      intip               gdsys          -           intip:DEVCONCENTER
 dlvision                     powerpc     ppc4xx      -                   gdsys
+dlvision-10g                 powerpc     ppc4xx      405ep               gdsys
 gdppc440etx                  powerpc     ppc4xx      -                   gdsys
 intip                        powerpc     ppc4xx      intip               gdsys          -           intip:INTIB
 io                           powerpc     ppc4xx      405ep               gdsys
diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
new file mode 100644
index 0000000..4972f76
--- /dev/null
+++ b/include/configs/dlvision-10g.h
@@ -0,0 +1,322 @@ 
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP		1	/* this is a PPC405 CPU */
+#define CONFIG_4xx		1	/*  member of PPC4xx family */
+#define CONFIG_DLVISION_10G	1	/*  on a DLVision-10G board */
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME		dlvsion-10g
+#define CONFIG_IDENT_STRING	" dlvision-10g 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll   */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_AMCC_DEF_ENV						\
+	CONFIG_AMCC_DEF_ENV_POWERPC					\
+	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
+	"kernel_addr=fc000000\0"					\
+	"fdt_addr=fc1e0000\0"						\
+	"ramdisk_addr=fc200000\0"					\
+	""
+
+#define CONFIG_PHY_ADDR		4	/* PHY address			*/
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR	0xc	/* EMAC1 PHY address		*/
+#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL             3	/* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC          66	/* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ *    baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#undef  CONFIG_SYS_EXT_SERIAL_CLOCK	/* external serial clock */
+#undef  CONFIG_SYS_405_UART_ERRATA_59	/* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD		691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63		1	/* National LM63	*/
+#define CONFIG_DTT_SENSORS	{ 0 }	/* Sensor addresses	*/
+#define CONFIG_DTT_PWM_LOOKUPTABLE	\
+		{ { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT	0xa10
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
+#define CONFIG_SYS_FPGA1_BASE		0x7f200000
+#define CONFIG_SYS_LATCH_BASE		0x7f300000
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+	(k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+	(k ? 0x2000 : 0x10000)
+
+#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
+#define CONFIG_SYS_FPGA_RFL_HIGH	0x007e
+
+#define CONFIG_SYS_FPGA_OSD_BASE	0x0200
+#define CONFIG_SYS_FPGA_OSD_MEM		0x0800
+
+#define CONFIG_SYS_FPGA_COUNT		2
+
+#define CONFIG_SYS_LATCH0_RESET		0xffff
+#define CONFIG_SYS_LATCH0_BOOT		0xffff
+#define CONFIG_SYS_LATCH1_RESET		0xffcf
+#define CONFIG_SYS_LATCH1_BOOT		0xffff
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
+#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO	/* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector */
+#define CONFIG_ENV_ADDR		((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO	Alternate1	*/ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1	TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2	TS2E */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3	TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4	TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO5	TS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6	TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1      }, /* GPIO7	TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8	TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM	1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128  /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP	(EBC_BXAP_BME_ENABLED		|	\
+				 EBC_BXAP_FWT_ENCODE(8)		|	\
+				 EBC_BXAP_BWT_ENCODE(7)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(2)		|	\
+				 EBC_BXAP_WBF_ENCODE(2)		|	\
+				 EBC_BXAP_TH_ENCODE(4)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+				 EBC_BXCR_BS_64MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (FPGA0) */
+#define CONFIG_SYS_EBC_PB1AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(5)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(0)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 2 (FPGA1) */
+#define CONFIG_SYS_EBC_PB2AP	(EBC_BXAP_BME_DISABLED		|	\
+				 EBC_BXAP_TWT_ENCODE(6)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(2)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(0)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP	(EBC_BXAP_BME_ENABLED		|	\
+				 EBC_BXAP_FWT_ENCODE(8)		|	\
+				 EBC_BXAP_BWT_ENCODE(4)		|	\
+				 EBC_BXAP_BCE_DISABLE		|	\
+				 EBC_BXAP_BCT_2TRANS		|	\
+				 EBC_BXAP_CSN_ENCODE(0)		|	\
+				 EBC_BXAP_OEN_ENCODE(1)		|	\
+				 EBC_BXAP_WBN_ENCODE(1)		|	\
+				 EBC_BXAP_WBF_ENCODE(1)		|	\
+				 EBC_BXAP_TH_ENCODE(2)		|	\
+				 EBC_BXAP_RE_DISABLED		|	\
+				 EBC_BXAP_SOR_NONDELAYED	|	\
+				 EBC_BXAP_BEM_WRITEONLY		|	\
+				 EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR	(EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+				 EBC_BXCR_BS_1MB		|	\
+				 EBC_BXCR_BU_RW			|	\
+				 EBC_BXCR_BW_16BIT)
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_ICS8N3QV01
+#define CONFIG_SYS_SIL1178
+#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/io.h b/include/configs/io.h
index a66c704..e287ad9 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -229,14 +229,19 @@ 
 #define CONFIG_SYS_EBC_PB1CR		0x7f318000
 
 /* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02025080
 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 #define CONFIG_SYS_EBC_PB2CR		0x7f11a000
 
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
+
 #define CONFIG_SYS_FPGA_RFL_LOW		0x0000
 #define CONFIG_SYS_FPGA_RFL_HIGH	0x3ffe
 
+#define CONFIG_SYS_FPGA_COUNT		1
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0xa2015480
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 5e61b11..c713915 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -131,6 +131,12 @@  int fpga_gpio_get(int pin);
 #define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
 
 /*
+ * OSD hardware
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+
+/*
  * FLASH organization
  */
 #define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible	*/
@@ -231,14 +237,22 @@  int fpga_gpio_get(int pin);
 #define CONFIG_SYS_EBC_PB1AP		0x92015480
 #define CONFIG_SYS_EBC_PB1CR		0xFB858000
 
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+/* Memory Bank 2 (FPGA0) initialization */
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02825080
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x1a000)
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA0_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
 
 #define CONFIG_SYS_FPGA_RFL_LOW		0x0000
 #define CONFIG_SYS_FPGA_RFL_HIGH	0x00fe
 
+#define CONFIG_SYS_FPGA_OSD_BASE	0x0100
+#define CONFIG_SYS_FPGA_OSD_MEM		0x0800
+
+#define CONFIG_SYS_FPGA_COUNT		1
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0x02025080
@@ -249,4 +263,11 @@  int fpga_gpio_get(int pin);
 #define CONFIG_SYS_LATCH1_RESET		0xffff
 #define CONFIG_SYS_LATCH1_BOOT		0xffff
 
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
+
 #endif	/* __CONFIG_H */