===================================================================
@@ -1449,8 +1449,7 @@ sparc_option_override (void)
MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC },
/* UltraSPARC M8 */
{ "m8", MASK_ISA,
- MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC
- |MASK_VIS4B }
+ MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC|MASK_VIS4B }
};
const struct cpu_table *cpu;
unsigned int i;
@@ -1489,6 +1488,11 @@ sparc_option_override (void)
}
}
+ /* Enable the FsMULd instruction by default if not explicitly specified by
+ the user. It may be later disabled by the CPU (explicitly or not). */
+ if (TARGET_FPU && !(target_flags_explicit & MASK_FSMULD))
+ target_flags |= MASK_FSMULD;
+
if (TARGET_DEBUG_OPTIONS)
{
dump_target_flags("Initial target_flags", target_flags);
@@ -1513,12 +1517,6 @@ sparc_option_override (void)
target_flags |= MASK_LONG_DOUBLE_128;
}
- /* Enable the FsMULd instruction by default if not explicitly configured by
- the user. It may be later disabled by the CPU target flags or if
- !TARGET_FPU. */
- if (!(target_flags_explicit & MASK_FSMULD))
- target_flags |= MASK_FSMULD;
-
/* Code model selection. */
sparc_cmodel = SPARC_DEFAULT_CMODEL;
@@ -1540,7 +1538,7 @@ sparc_option_override (void)
sparc_cmodel = cmodel->value;
}
else
- error ("-mcmodel= is not supported on 32 bit systems");
+ error ("-mcmodel= is not supported on 32-bit systems");
}
/* Check that -fcall-saved-REG wasn't specified for out registers. */
@@ -1551,7 +1549,7 @@ sparc_option_override (void)
call_used_regs [i] = 1;
}
- /* Set the default CPU. */
+ /* Set the default CPU if no -mcpu option was specified. */
if (!global_options_set.x_sparc_cpu_and_features)
{
for (def = &cpu_default[0]; def->cpu != -1; ++def)
@@ -1561,6 +1559,7 @@ sparc_option_override (void)
sparc_cpu_and_features = def->processor;
}
+ /* Set the default CPU if no -mtune option was specified. */
if (!global_options_set.x_sparc_cpu)
sparc_cpu = sparc_cpu_and_features;
@@ -1569,8 +1568,6 @@ sparc_option_override (void)
if (TARGET_DEBUG_OPTIONS)
{
fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name);
- fprintf (stderr, "sparc_cpu: %s\n",
- cpu_table[(int) sparc_cpu].name);
dump_target_flags ("cpu->disable", cpu->disable);
dump_target_flags ("cpu->enable", cpu->enable);
}
@@ -1613,7 +1610,7 @@ sparc_option_override (void)
/* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
FPU is disabled. */
- if (! TARGET_FPU)
+ if (!TARGET_FPU)
target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS4
| MASK_VIS4B | MASK_FMAF | MASK_FSMULD);
@@ -1626,18 +1623,18 @@ sparc_option_override (void)
}
/* -mvis also implies -mv8plus on 32-bit. */
- if (TARGET_VIS && ! TARGET_ARCH64)
+ if (TARGET_VIS && !TARGET_ARCH64)
target_flags |= MASK_V8PLUS;
- /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
+ /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
if (TARGET_V9 && TARGET_ARCH32)
target_flags |= MASK_DEPRECATED_V8_INSNS;
- /* V8PLUS requires V9, makes no sense in 64 bit mode. */
- if (! TARGET_V9 || TARGET_ARCH64)
+ /* V8PLUS requires V9 and makes no sense in 64-bit mode. */
+ if (!TARGET_V9 || TARGET_ARCH64)
target_flags &= ~MASK_V8PLUS;
- /* Don't use stack biasing in 32 bit mode. */
+ /* Don't use stack biasing in 32-bit mode. */
if (TARGET_ARCH32)
target_flags &= ~MASK_STACK_BIAS;
@@ -4975,7 +4972,7 @@ enum sparc_mode_class {
??? Note that, despite the settings, non-double-aligned parameter
registers can hold double-word quantities in 32-bit mode. */
-/* This points to either the 32 bit or the 64 bit version. */
+/* This points to either the 32-bit or the 64-bit version. */
const int *hard_regno_mode_classes;
static const int hard_32bit_mode_classes[] = {
@@ -7309,7 +7306,7 @@ sparc_function_arg_advance (cumulative_args_t cum_
}
/* Handle the FUNCTION_ARG_PADDING macro.
- For the 64 bit ABI structs are always stored left shifted in their
+ For the 64-bit ABI structs are always stored left shifted in their
argument slot. */
enum direction
@@ -8428,7 +8425,7 @@ output_v9branch (rtx op, rtx dest, int reg, int la
if (reversed ^ far)
code = reverse_condition (code);
- /* Only 64 bit versions of these instructions exist. */
+ /* Only 64-bit versions of these instructions exist. */
gcc_assert (mode == DImode);
/* Start by writing the branch condition. */
@@ -8857,7 +8854,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx depe
return 0;
/* The first offset must be evenly divisible by 8 to ensure the
- address is 64 bit aligned. */
+ address is 64-bit aligned. */
if (offset1 % 8 != 0)
return 0;