From patchwork Wed Jan 19 09:27:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 79437 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 0E309B7088 for ; Wed, 19 Jan 2011 20:27:44 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A4541280EB; Wed, 19 Jan 2011 10:27:41 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cCacFfLDug7F; Wed, 19 Jan 2011 10:27:41 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 211EB280B5; Wed, 19 Jan 2011 10:27:40 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 302D2280B5 for ; Wed, 19 Jan 2011 10:27:38 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ffCHBCQ25jwy for ; Wed, 19 Jan 2011 10:27:35 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by theia.denx.de (Postfix) with ESMTPS id 0AA3F280B2 for ; Wed, 19 Jan 2011 10:27:33 +0100 (CET) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p0J9RUTV017608 for ; Wed, 19 Jan 2011 03:27:30 -0600 From: Kumar Gala To: u-boot@lists.denx.de Date: Wed, 19 Jan 2011 03:27:30 -0600 Message-Id: <1295429250-25788-1-git-send-email-galak@kernel.crashing.org> X-Mailer: git-send-email 1.6.0.6 Subject: [U-Boot] [PATCH] powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala Acked-by: Wolfgang Denk --- * I know its late for such a patch, but I think it best to introduce right after the merge window closes so that patches for the next release deal with it and I didn't require everyone else to deal with for this merge window Also I think its a beneficial cleanup to address several long standing code duplication problems. arch/powerpc/include/asm/config.h | 41 ++----- arch/powerpc/include/asm/config_mpc85xx.h | 187 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc86xx.h | 38 ++++++ drivers/misc/fsl_law.c | 22 +---- include/configs/P4080DS.h | 16 --- 5 files changed, 236 insertions(+), 68 deletions(-) create mode 100644 arch/powerpc/include/asm/config_mpc85xx.h create mode 100644 arch/powerpc/include/asm/config_mpc86xx.h diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 1b9c47b..2b6b233 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -21,6 +21,14 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#ifdef CONFIG_MPC85xx +#include +#endif + +#ifdef CONFIG_MPC86xx +#include +#endif + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_SYS_BOOT_GET_CMDLINE @@ -43,19 +51,7 @@ #endif #endif -#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ - defined(CONFIG_P1021) || defined(CONFIG_P1022) || \ - defined(CONFIG_P2020) || defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 -#elif defined(CONFIG_PPC_P2040) -#define CONFIG_MAX_CPUS 4 -#elif defined(CONFIG_PPC_P3041) -#define CONFIG_MAX_CPUS 4 -#elif defined(CONFIG_PPC_P4080) -#define CONFIG_MAX_CPUS 8 -#elif defined(CONFIG_PPC_P5020) -#define CONFIG_MAX_CPUS 2 -#else +#ifndef CONFIG_MAX_CPUS #define CONFIG_MAX_CPUS 1 #endif @@ -69,30 +65,13 @@ #endif #endif -/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ -#if defined(CONFIG_TSEC_ENET) && \ - (defined(CONFIG_P1010) || defined(CONFIG_P1014) || \ - defined(CONFIG_P1020) || defined(CONFIG_P1011)) -#define CONFIG_TSECV2 -#endif - /* * SEC (crypto unit) major compatible version determination */ -#if defined(CONFIG_FSL_CORENET) || \ - defined(CONFIG_P1010) || defined(CONFIG_P1014) -#define CONFIG_SYS_FSL_SEC_COMPAT 4 -#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx) +#if defined(CONFIG_MPC83xx) #define CONFIG_SYS_FSL_SEC_COMPAT 2 #endif -/* Number of TLB CAM entries we have on FSL Book-E chips */ -#if defined(CONFIG_E500MC) -#define CONFIG_SYS_NUM_TLBCAMS 64 -#elif defined(CONFIG_E500) -#define CONFIG_SYS_NUM_TLBCAMS 16 -#endif - /* Since so many PPC SOCs have a semi-common LBC, define this here */ #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC83xx) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h new file mode 100644 index 0000000..8ba6c7e --- /dev/null +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -0,0 +1,187 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_MPC85xx_CONFIG_H_ +#define _ASM_MPC85xx_CONFIG_H_ + +/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ + +/* Number of TLB CAM entries we have on FSL Book-E chips */ +#if defined(CONFIG_E500MC) +#define CONFIG_SYS_NUM_TLBCAMS 64 +#elif defined(CONFIG_E500) +#define CONFIG_SYS_NUM_TLBCAMS 16 +#endif + +#if defined(CONFIG_MPC8536) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8540) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 8 + +#elif defined(CONFIG_MPC8541) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8544) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8548) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8555) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8560) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 8 + +#elif defined(CONFIG_MPC8568) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8569) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_MPC8572) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1010) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_P1011) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1012) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1013) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1014) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_P1020) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1021) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P1022) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P2010) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_P2020) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_FSL_SEC_COMPAT 2 + +#elif defined(CONFIG_PPC_P2040) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_PPC_P3041) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_PPC_P4040) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_PPC_P4080) +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 2 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM2_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_ERRATUM_CPC_A002 +#define CONFIG_SYS_FSL_ERRATUM_CPC_A003 +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC136 +#define CONFIG_SYS_P4080_ERRATUM_CPU22 +#define CONFIG_SYS_P4080_ERRATUM_SERDES8 + +#elif defined(CONFIG_PPC_P5010) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#elif defined(CONFIG_PPC_P5020) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 + +#else +#error Processor type not defined for this platform +#endif + +#endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h new file mode 100644 index 0000000..c5c1ef4 --- /dev/null +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -0,0 +1,38 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_MPC86xx_CONFIG_H_ +#define _ASM_MPC86xx_CONFIG_H_ + +/* SoC specific defines for Freescale MPC86xx processors */ + +#if defined(CONFIG_MPC8610) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_SYS_FSL_NUM_LAWS 10 + +#elif defined(CONFIG_MPC8641) +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_LAWS 10 + +#else +#error Processor type not defined for this platform +#endif + +#endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 76f4688..63c08bf 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -29,27 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; -/* number of LAWs in the hw implementation */ -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) -#define FSL_HW_NUM_LAWS 8 -#elif defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ - defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569) || \ - defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610) -#define FSL_HW_NUM_LAWS 10 -#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \ - defined(CONFIG_P1010) || defined(CONFIG_P1014) || \ - defined(CONFIG_P1011) || defined(CONFIG_P1020) || \ - defined(CONFIG_P1012) || defined(CONFIG_P1021) || \ - defined(CONFIG_P1013) || defined(CONFIG_P1022) || \ - defined(CONFIG_P2010) || defined(CONFIG_P2020) -#define FSL_HW_NUM_LAWS 12 -#elif defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P3041) || \ - defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P5020) -#define FSL_HW_NUM_LAWS 32 -#else -#error FSL_HW_NUM_LAWS not defined for this platform -#endif +#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS #ifdef CONFIG_FSL_CORENET #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR) diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index 5c818c9..49f7c53 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -26,23 +26,7 @@ #define CONFIG_P4080DS #define CONFIG_PHYS_64BIT #define CONFIG_PPC_P4080 -#define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_SYS_NUM_FM2_DTSEC 4 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC135 -#define CONFIG_SYS_FSL_ERRATUM_ESDHC136 - -#define CONFIG_SYS_P4080_ERRATUM_CPU22 -#define CONFIG_SYS_FSL_ERRATUM_CPC_A002 -#define CONFIG_SYS_FSL_ERRATUM_CPC_A003 -#define CONFIG_SYS_P4080_ERRATUM_SERDES8 -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 - #include "corenet_ds.h"