Patchwork [U-Boot] powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headers

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Submitter Kumar Gala
Date Jan. 19, 2011, 9:27 a.m.
Message ID <1295429250-25788-1-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/79437/
State Accepted
Delegated to: Kumar Gala
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Comments

Kumar Gala - Jan. 19, 2011, 9:27 a.m.
Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.

Eventually this should be handled by Kconfig & defconfigs

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
* I know its late for such a patch, but I think it best to introduce right after
  the merge window closes so that patches for the next release deal with it and
  I didn't require everyone else to deal with for this merge window

  Also I think its a beneficial cleanup to address several long standing
  code duplication problems.

 arch/powerpc/include/asm/config.h         |   41 ++-----
 arch/powerpc/include/asm/config_mpc85xx.h |  187 +++++++++++++++++++++++++++++
 arch/powerpc/include/asm/config_mpc86xx.h |   38 ++++++
 drivers/misc/fsl_law.c                    |   22 +----
 include/configs/P4080DS.h                 |   16 ---
 5 files changed, 236 insertions(+), 68 deletions(-)
 create mode 100644 arch/powerpc/include/asm/config_mpc85xx.h
 create mode 100644 arch/powerpc/include/asm/config_mpc86xx.h
Kumar Gala - Jan. 19, 2011, 9:33 a.m.
Wolfgang,

Please take a look.  I'd like to see this go in for v2011.03 to clean up the both the order issue, but also establish a cleaner means to handle SoC specific defines for 85xx/86xx/QorIQ going forward.

(will be helpful for things like SoC specific errata not having to get put into every board config.h, as well as remove duplication in those files -- which can wait for post v2011.03).

- k

On Jan 19, 2011, at 3:27 AM, Kumar Gala wrote:

> Add new headers that capture common defines for a given SoC/processor
> rather than duplicating that information in board config.h and random
> other places.
> 
> Eventually this should be handled by Kconfig & defconfigs
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> * I know its late for such a patch, but I think it best to introduce right after
>  the merge window closes so that patches for the next release deal with it and
>  I didn't require everyone else to deal with for this merge window
> 
>  Also I think its a beneficial cleanup to address several long standing
>  code duplication problems.
> 
> arch/powerpc/include/asm/config.h         |   41 ++-----
> arch/powerpc/include/asm/config_mpc85xx.h |  187 +++++++++++++++++++++++++++++
> arch/powerpc/include/asm/config_mpc86xx.h |   38 ++++++
> drivers/misc/fsl_law.c                    |   22 +----
> include/configs/P4080DS.h                 |   16 ---
> 5 files changed, 236 insertions(+), 68 deletions(-)
> create mode 100644 arch/powerpc/include/asm/config_mpc85xx.h
> create mode 100644 arch/powerpc/include/asm/config_mpc86xx.h
> 
> diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
> index 1b9c47b..2b6b233 100644
> --- a/arch/powerpc/include/asm/config.h
> +++ b/arch/powerpc/include/asm/config.h
> @@ -21,6 +21,14 @@
> #ifndef _ASM_CONFIG_H_
> #define _ASM_CONFIG_H_
> 
> +#ifdef CONFIG_MPC85xx
> +#include <asm/config_mpc85xx.h>
> +#endif
> +
> +#ifdef CONFIG_MPC86xx
> +#include <asm/config_mpc86xx.h>
> +#endif
> +
> #define CONFIG_LMB
> #define CONFIG_SYS_BOOT_RAMDISK_HIGH
> #define CONFIG_SYS_BOOT_GET_CMDLINE
> @@ -43,19 +51,7 @@
> #endif
> #endif
> 
> -#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
> -	defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
> -	defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
> -#define CONFIG_MAX_CPUS		2
> -#elif defined(CONFIG_PPC_P2040)
> -#define CONFIG_MAX_CPUS		4
> -#elif defined(CONFIG_PPC_P3041)
> -#define CONFIG_MAX_CPUS		4
> -#elif defined(CONFIG_PPC_P4080)
> -#define CONFIG_MAX_CPUS		8
> -#elif defined(CONFIG_PPC_P5020)
> -#define CONFIG_MAX_CPUS		2
> -#else
> +#ifndef CONFIG_MAX_CPUS
> #define CONFIG_MAX_CPUS		1
> #endif
> 
> @@ -69,30 +65,13 @@
> #endif
> #endif
> 
> -/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
> -#if defined(CONFIG_TSEC_ENET) && \
> -    (defined(CONFIG_P1010) || defined(CONFIG_P1014) || \
> -     defined(CONFIG_P1020) || defined(CONFIG_P1011))
> -#define CONFIG_TSECV2
> -#endif
> -
> /*
>  * SEC (crypto unit) major compatible version determination
>  */
> -#if defined(CONFIG_FSL_CORENET) || \
> -    defined(CONFIG_P1010) || defined(CONFIG_P1014)
> -#define CONFIG_SYS_FSL_SEC_COMPAT	4
> -#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
> +#if defined(CONFIG_MPC83xx)
> #define CONFIG_SYS_FSL_SEC_COMPAT	2
> #endif
> 
> -/* Number of TLB CAM entries we have on FSL Book-E chips */
> -#if defined(CONFIG_E500MC)
> -#define CONFIG_SYS_NUM_TLBCAMS	64
> -#elif defined(CONFIG_E500)
> -#define CONFIG_SYS_NUM_TLBCAMS	16
> -#endif
> -
> /* Since so many PPC SOCs have a semi-common LBC, define this here */
> #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
> 	defined(CONFIG_MPC83xx)
> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
> new file mode 100644
> index 0000000..8ba6c7e
> --- /dev/null
> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> @@ -0,0 +1,187 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef _ASM_MPC85xx_CONFIG_H_
> +#define _ASM_MPC85xx_CONFIG_H_
> +
> +/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
> +
> +/* Number of TLB CAM entries we have on FSL Book-E chips */
> +#if defined(CONFIG_E500MC)
> +#define CONFIG_SYS_NUM_TLBCAMS		64
> +#elif defined(CONFIG_E500)
> +#define CONFIG_SYS_NUM_TLBCAMS		16
> +#endif
> +
> +#if defined(CONFIG_MPC8536)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_MPC8540) 
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		8
> +
> +#elif defined(CONFIG_MPC8541) 
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		8
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_MPC8544)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		10
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_MPC8548)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		10
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_MPC8555)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		8
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_MPC8560)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		8
> +
> +#elif defined(CONFIG_MPC8568)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		10
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_MPC8569)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		10
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_MPC8572)
> +#define CONFIG_MAX_CPUS			2
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_P1010)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT	4
> +
> +#elif defined(CONFIG_P1011)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_P1012)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_P1013)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_P1014)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT	4
> +
> +#elif defined(CONFIG_P1020)
> +#define CONFIG_MAX_CPUS			2
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_P1021)
> +#define CONFIG_MAX_CPUS			2
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_P1022)
> +#define CONFIG_MAX_CPUS			2
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_TSECV2
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_P2010)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_P2020)
> +#define CONFIG_MAX_CPUS			2
> +#define CONFIG_SYS_FSL_NUM_LAWS		12
> +#define CONFIG_SYS_FSL_SEC_COMPAT	2
> +
> +#elif defined(CONFIG_PPC_P2040)
> +#define CONFIG_MAX_CPUS			4
> +#define CONFIG_SYS_FSL_NUM_LAWS		32
> +#define CONFIG_SYS_FSL_SEC_COMPAT	4
> +
> +#elif defined(CONFIG_PPC_P3041)
> +#define CONFIG_MAX_CPUS			4
> +#define CONFIG_SYS_FSL_NUM_LAWS		32
> +#define CONFIG_SYS_FSL_SEC_COMPAT	4
> +
> +#elif defined(CONFIG_PPC_P4040)
> +#define CONFIG_MAX_CPUS			4
> +#define CONFIG_SYS_FSL_NUM_LAWS		32
> +#define CONFIG_SYS_FSL_SEC_COMPAT	4
> +
> +#elif defined(CONFIG_PPC_P4080)
> +#define CONFIG_MAX_CPUS			8
> +#define CONFIG_SYS_FSL_NUM_LAWS		32
> +#define CONFIG_SYS_FSL_SEC_COMPAT	4
> +#define CONFIG_SYS_NUM_FMAN		2
> +#define CONFIG_SYS_NUM_FM1_DTSEC	4
> +#define CONFIG_SYS_NUM_FM2_DTSEC	4
> +#define CONFIG_SYS_NUM_FM1_10GEC	1
> +#define CONFIG_SYS_NUM_FM2_10GEC	1
> +#define CONFIG_NUM_DDR_CONTROLLERS	2
> +#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
> +#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
> +#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
> +#define CONFIG_SYS_P4080_ERRATUM_CPU22
> +#define CONFIG_SYS_P4080_ERRATUM_SERDES8
> +
> +#elif defined(CONFIG_PPC_P5010)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		32
> +#define CONFIG_SYS_FSL_SEC_COMPAT	4
> +
> +#elif defined(CONFIG_PPC_P5020)
> +#define CONFIG_MAX_CPUS			2
> +#define CONFIG_SYS_FSL_NUM_LAWS		32
> +#define CONFIG_SYS_FSL_SEC_COMPAT	4
> +
> +#else
> +#error Processor type not defined for this platform
> +#endif
> +
> +#endif /* _ASM_MPC85xx_CONFIG_H_ */
> diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
> new file mode 100644
> index 0000000..c5c1ef4
> --- /dev/null
> +++ b/arch/powerpc/include/asm/config_mpc86xx.h
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright 2011 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef _ASM_MPC86xx_CONFIG_H_
> +#define _ASM_MPC86xx_CONFIG_H_
> +
> +/* SoC specific defines for Freescale MPC86xx processors */
> +
> +#if defined(CONFIG_MPC8610)
> +#define CONFIG_MAX_CPUS			1
> +#define CONFIG_SYS_FSL_NUM_LAWS		10
> +
> +#elif defined(CONFIG_MPC8641) 
> +#define CONFIG_MAX_CPUS			2
> +#define CONFIG_SYS_FSL_NUM_LAWS		10
> +
> +#else
> +#error Processor type not defined for this platform
> +#endif
> +
> +#endif /* _ASM_MPC85xx_CONFIG_H_ */
> diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
> index 76f4688..63c08bf 100644
> --- a/drivers/misc/fsl_law.c
> +++ b/drivers/misc/fsl_law.c
> @@ -29,27 +29,7 @@
> 
> DECLARE_GLOBAL_DATA_PTR;
> 
> -/* number of LAWs in the hw implementation */
> -#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
> -    defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
> -#define FSL_HW_NUM_LAWS 8
> -#elif defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
> -      defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569) || \
> -      defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
> -#define FSL_HW_NUM_LAWS 10
> -#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
> -      defined(CONFIG_P1010) || defined(CONFIG_P1014) || \
> -      defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
> -      defined(CONFIG_P1012) || defined(CONFIG_P1021) || \
> -      defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
> -      defined(CONFIG_P2010) || defined(CONFIG_P2020)
> -#define FSL_HW_NUM_LAWS 12
> -#elif defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P3041) || \
> -      defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P5020)
> -#define FSL_HW_NUM_LAWS 32
> -#else
> -#error FSL_HW_NUM_LAWS not defined for this platform
> -#endif
> +#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
> 
> #ifdef CONFIG_FSL_CORENET
> #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
> diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
> index 5c818c9..49f7c53 100644
> --- a/include/configs/P4080DS.h
> +++ b/include/configs/P4080DS.h
> @@ -26,23 +26,7 @@
> #define CONFIG_P4080DS
> #define CONFIG_PHYS_64BIT
> #define CONFIG_PPC_P4080
> -#define CONFIG_SYS_NUM_FMAN		2
> -#define CONFIG_SYS_NUM_FM1_DTSEC	4
> -#define CONFIG_SYS_NUM_FM2_DTSEC	4
> -#define CONFIG_SYS_NUM_FM1_10GEC	1
> -#define CONFIG_SYS_NUM_FM2_10GEC	1
> -#define CONFIG_NUM_DDR_CONTROLLERS	2
> 
> #define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
> 
> -#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
> -#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
> -#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
> -
> -#define CONFIG_SYS_P4080_ERRATUM_CPU22
> -#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
> -#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
> -#define CONFIG_SYS_P4080_ERRATUM_SERDES8
> -#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
> -
> #include "corenet_ds.h"
> -- 
> 1.7.2.3
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
Wolfgang Denk - Jan. 19, 2011, 9:40 p.m.
Dear Kumar Gala,

In message <1295429250-25788-1-git-send-email-galak@kernel.crashing.org> you wrote:
> Add new headers that capture common defines for a given SoC/processor
> rather than duplicating that information in board config.h and random
> other places.
> 
> Eventually this should be handled by Kconfig & defconfigs
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> * I know its late for such a patch, but I think it best to introduce right after
>   the merge window closes so that patches for the next release deal with it and
>   I didn't require everyone else to deal with for this merge window
> 
>   Also I think its a beneficial cleanup to address several long standing
>   code duplication problems.
> 
>  arch/powerpc/include/asm/config.h         |   41 ++-----
>  arch/powerpc/include/asm/config_mpc85xx.h |  187 +++++++++++++++++++++++++++++
>  arch/powerpc/include/asm/config_mpc86xx.h |   38 ++++++
>  drivers/misc/fsl_law.c                    |   22 +----
>  include/configs/P4080DS.h                 |   16 ---
>  5 files changed, 236 insertions(+), 68 deletions(-)
>  create mode 100644 arch/powerpc/include/asm/config_mpc85xx.h
>  create mode 100644 arch/powerpc/include/asm/config_mpc86xx.h

Acked-by: Wolfgang Denk <wd@denx.de>

Best regards,

Wolfgang Denk
Kumar Gala - Jan. 19, 2011, 9:51 p.m.
On Jan 19, 2011, at 3:40 PM, Wolfgang Denk wrote:

> Dear Kumar Gala,
> 
> In message <1295429250-25788-1-git-send-email-galak@kernel.crashing.org> you wrote:
>> Add new headers that capture common defines for a given SoC/processor
>> rather than duplicating that information in board config.h and random
>> other places.
>> 
>> Eventually this should be handled by Kconfig & defconfigs
>> 
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> ---
>> * I know its late for such a patch, but I think it best to introduce right after
>>  the merge window closes so that patches for the next release deal with it and
>>  I didn't require everyone else to deal with for this merge window
>> 
>>  Also I think its a beneficial cleanup to address several long standing
>>  code duplication problems.
>> 
>> arch/powerpc/include/asm/config.h         |   41 ++-----
>> arch/powerpc/include/asm/config_mpc85xx.h |  187 +++++++++++++++++++++++++++++
>> arch/powerpc/include/asm/config_mpc86xx.h |   38 ++++++
>> drivers/misc/fsl_law.c                    |   22 +----
>> include/configs/P4080DS.h                 |   16 ---
>> 5 files changed, 236 insertions(+), 68 deletions(-)
>> create mode 100644 arch/powerpc/include/asm/config_mpc85xx.h
>> create mode 100644 arch/powerpc/include/asm/config_mpc86xx.h
> 
> Acked-by: Wolfgang Denk <wd@denx.de>

applied to 85xx

- k

Patch

diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index 1b9c47b..2b6b233 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -21,6 +21,14 @@ 
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#ifdef CONFIG_MPC85xx
+#include <asm/config_mpc85xx.h>
+#endif
+
+#ifdef CONFIG_MPC86xx
+#include <asm/config_mpc86xx.h>
+#endif
+
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
 #define CONFIG_SYS_BOOT_GET_CMDLINE
@@ -43,19 +51,7 @@ 
 #endif
 #endif
 
-#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
-	defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
-	defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
-#define CONFIG_MAX_CPUS		2
-#elif defined(CONFIG_PPC_P2040)
-#define CONFIG_MAX_CPUS		4
-#elif defined(CONFIG_PPC_P3041)
-#define CONFIG_MAX_CPUS		4
-#elif defined(CONFIG_PPC_P4080)
-#define CONFIG_MAX_CPUS		8
-#elif defined(CONFIG_PPC_P5020)
-#define CONFIG_MAX_CPUS		2
-#else
+#ifndef CONFIG_MAX_CPUS
 #define CONFIG_MAX_CPUS		1
 #endif
 
@@ -69,30 +65,13 @@ 
 #endif
 #endif
 
-/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
-#if defined(CONFIG_TSEC_ENET) && \
-    (defined(CONFIG_P1010) || defined(CONFIG_P1014) || \
-     defined(CONFIG_P1020) || defined(CONFIG_P1011))
-#define CONFIG_TSECV2
-#endif
-
 /*
  * SEC (crypto unit) major compatible version determination
  */
-#if defined(CONFIG_FSL_CORENET) || \
-    defined(CONFIG_P1010) || defined(CONFIG_P1014)
-#define CONFIG_SYS_FSL_SEC_COMPAT	4
-#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
+#if defined(CONFIG_MPC83xx)
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #endif
 
-/* Number of TLB CAM entries we have on FSL Book-E chips */
-#if defined(CONFIG_E500MC)
-#define CONFIG_SYS_NUM_TLBCAMS	64
-#elif defined(CONFIG_E500)
-#define CONFIG_SYS_NUM_TLBCAMS	16
-#endif
-
 /* Since so many PPC SOCs have a semi-common LBC, define this here */
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
 	defined(CONFIG_MPC83xx)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
new file mode 100644
index 0000000..8ba6c7e
--- /dev/null
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -0,0 +1,187 @@ 
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_MPC85xx_CONFIG_H_
+#define _ASM_MPC85xx_CONFIG_H_
+
+/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
+
+/* Number of TLB CAM entries we have on FSL Book-E chips */
+#if defined(CONFIG_E500MC)
+#define CONFIG_SYS_NUM_TLBCAMS		64
+#elif defined(CONFIG_E500)
+#define CONFIG_SYS_NUM_TLBCAMS		16
+#endif
+
+#if defined(CONFIG_MPC8536)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_MPC8540) 
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		8
+
+#elif defined(CONFIG_MPC8541) 
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_MPC8544)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		10
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_MPC8548)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		10
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_MPC8555)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		8
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_MPC8560)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		8
+
+#elif defined(CONFIG_MPC8568)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		10
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_MPC8569)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		10
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_MPC8572)
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_P1010)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+
+#elif defined(CONFIG_P1011)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_P1012)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_P1013)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_P1014)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+
+#elif defined(CONFIG_P1020)
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_P1021)
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_P1022)
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_P2010)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_P2020)
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_SYS_FSL_SEC_COMPAT	2
+
+#elif defined(CONFIG_PPC_P2040)
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+
+#elif defined(CONFIG_PPC_P3041)
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+
+#elif defined(CONFIG_PPC_P4040)
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+
+#elif defined(CONFIG_PPC_P4080)
+#define CONFIG_MAX_CPUS			8
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	4
+#define CONFIG_SYS_NUM_FM2_DTSEC	4
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
+#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
+#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#define CONFIG_SYS_P4080_ERRATUM_CPU22
+#define CONFIG_SYS_P4080_ERRATUM_SERDES8
+
+#elif defined(CONFIG_PPC_P5010)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+
+#elif defined(CONFIG_PPC_P5020)
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+
+#else
+#error Processor type not defined for this platform
+#endif
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
new file mode 100644
index 0000000..c5c1ef4
--- /dev/null
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -0,0 +1,38 @@ 
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_MPC86xx_CONFIG_H_
+#define _ASM_MPC86xx_CONFIG_H_
+
+/* SoC specific defines for Freescale MPC86xx processors */
+
+#if defined(CONFIG_MPC8610)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_SYS_FSL_NUM_LAWS		10
+
+#elif defined(CONFIG_MPC8641) 
+#define CONFIG_MAX_CPUS			2
+#define CONFIG_SYS_FSL_NUM_LAWS		10
+
+#else
+#error Processor type not defined for this platform
+#endif
+
+#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 76f4688..63c08bf 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -29,27 +29,7 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* number of LAWs in the hw implementation */
-#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
-    defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
-#define FSL_HW_NUM_LAWS 8
-#elif defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
-      defined(CONFIG_MPC8568) || defined(CONFIG_MPC8569) || \
-      defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
-#define FSL_HW_NUM_LAWS 10
-#elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
-      defined(CONFIG_P1010) || defined(CONFIG_P1014) || \
-      defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
-      defined(CONFIG_P1012) || defined(CONFIG_P1021) || \
-      defined(CONFIG_P1013) || defined(CONFIG_P1022) || \
-      defined(CONFIG_P2010) || defined(CONFIG_P2020)
-#define FSL_HW_NUM_LAWS 12
-#elif defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P3041) || \
-      defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P5020)
-#define FSL_HW_NUM_LAWS 32
-#else
-#error FSL_HW_NUM_LAWS not defined for this platform
-#endif
+#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
 
 #ifdef CONFIG_FSL_CORENET
 #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
index 5c818c9..49f7c53 100644
--- a/include/configs/P4080DS.h
+++ b/include/configs/P4080DS.h
@@ -26,23 +26,7 @@ 
 #define CONFIG_P4080DS
 #define CONFIG_PHYS_64BIT
 #define CONFIG_PPC_P4080
-#define CONFIG_SYS_NUM_FMAN		2
-#define CONFIG_SYS_NUM_FM1_DTSEC	4
-#define CONFIG_SYS_NUM_FM2_DTSEC	4
-#define CONFIG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_SYS_NUM_FM2_10GEC	1
-#define CONFIG_NUM_DDR_CONTROLLERS	2
 
 #define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
 
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
-
-#define CONFIG_SYS_P4080_ERRATUM_CPU22
-#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
-#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
-#define CONFIG_SYS_P4080_ERRATUM_SERDES8
-#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
-
 #include "corenet_ds.h"