Patchwork [U-Boot] ppc/85xx:Fix compile err when PCI disabled on P1_P2_RDB

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Submitter Prabhakar Kushwaha
Date Jan. 19, 2011, 7:25 a.m.
Message ID <1295421916-21231-1-git-send-email-prabhakar@freescale.com>
Download mbox | patch
Permalink /patch/79424/
State Accepted
Commit b7070904327d10eb789ccafa4622659ffaa6645c
Delegated to: Kumar Gala
Headers show

Comments

Prabhakar Kushwaha - Jan. 19, 2011, 7:25 a.m.
u-boot cannot be compiled after disabling CONFIG_PCI.

Place PCI related codes under #ifdef CONFIG_PCI

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
 Based of http://git.denx.de/u-boot.git (branch master) 

 Top commit:
 commit 3f1266d6d5bf14ea7248544db8406d308c6bfa7c
Author: Loïc Minier <loic.minier@linaro.org>
Date:   Tue Jan 4 02:32:36 2011 +0100

    Escape minus signs in manpage
    
 board/freescale/p1_p2_rdb/p1_p2_rdb.c |    4 +++-
 board/freescale/p1_p2_rdb/tlb.c       |    4 +++-
 include/configs/P1_P2_RDB.h           |   13 ++++++++-----
 3 files changed, 14 insertions(+), 7 deletions(-)
Kumar Gala - Jan. 20, 2011, 4:38 a.m.
On Jan 19, 2011, at 1:25 AM, Prabhakar Kushwaha wrote:

> u-boot cannot be compiled after disabling CONFIG_PCI.
> 
> Place PCI related codes under #ifdef CONFIG_PCI
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Based of http://git.denx.de/u-boot.git (branch master) 
> 
> Top commit:
> commit 3f1266d6d5bf14ea7248544db8406d308c6bfa7c
> Author: Loïc Minier <loic.minier@linaro.org>
> Date:   Tue Jan 4 02:32:36 2011 +0100
> 
>    Escape minus signs in manpage
> 
> board/freescale/p1_p2_rdb/p1_p2_rdb.c |    4 +++-
> board/freescale/p1_p2_rdb/tlb.c       |    4 +++-
> include/configs/P1_P2_RDB.h           |   13 ++++++++-----
> 3 files changed, 14 insertions(+), 7 deletions(-)

applied to 85xx

- k

Patch

diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 440fcb9..0780942 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -222,7 +222,9 @@  void ft_board_setup(void *blob, bd_t *bd)
 	base = getenv_bootm_low();
 	size = getenv_bootm_size();
 
+#if defined(CONFIG_PCI)
 	ft_pci_board_setup(blob);
+#endif /* #if defined(CONFIG_PCI) */
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 }
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index 93d0bf7..b85c268 100644
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -58,6 +58,7 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 			0, 2, BOOKE_PAGESZ_16M, 1),
 
+#if defined(CONFIG_PCI)
 	/* *I*G* - PCI */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -68,6 +69,7 @@  struct fsl_e_tlb_entry tlb_table[] = {
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 			0, 4, BOOKE_PAGESZ_256K, 1),
 
+#endif /* #if defined(CONFIG_PCI) */
 	/* *I*G - NAND */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 80b0b40..033ee1f 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -77,17 +77,23 @@ 
 #define CONFIG_E500		1	/* BOOKE e500 family */
 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/P1020/P2020,etc*/
 #define CONFIG_FSL_ELBC		1	/* Enable eLBC Support */
+
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#if defined(CONFIG_PCI)
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+#endif /* #if defined(CONFIG_PCI) */
 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
+#if defined(CONFIG_PCI)
 #define CONFIG_E1000		1	/*  E1000 pci Ethernet card*/
+#endif
+
 #ifndef __ASSEMBLY__
 extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
@@ -358,6 +364,7 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
  */
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
+#if defined(CONFIG_PCI)
 #define CONFIG_SYS_PCIE2_NAME		"Slot 1"
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
@@ -379,8 +386,6 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc30000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
-#if defined(CONFIG_PCI)
-#define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
@@ -399,11 +404,9 @@  extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #endif	/* CONFIG_PCI */
 
-#if defined(CONFIG_TSEC_ENET)
-#ifndef CONFIG_NET_MULTI
 #define CONFIG_NET_MULTI	1
-#endif
 
+#if defined(CONFIG_TSEC_ENET)
 #define CONFIG_MII		1	/* MII PHY management */
 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
 #define CONFIG_TSEC1	1