===================================================================
@@ -55,8 +55,7 @@
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_HTM \
| OPTION_MASK_QUAD_MEMORY \
- | OPTION_MASK_QUAD_MEMORY_ATOMIC \
- | OPTION_MASK_VSX_SMALL_INTEGER)
+ | OPTION_MASK_QUAD_MEMORY_ATOMIC)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
@@ -75,8 +74,7 @@
#define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_VECTOR \
- | OPTION_MASK_DIRECT_MOVE \
- | OPTION_MASK_VSX_SMALL_INTEGER)
+ | OPTION_MASK_DIRECT_MOVE)
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
@@ -96,7 +94,6 @@
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FLOAT128_TYPE \
| OPTION_MASK_P8_VECTOR \
- | OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
@@ -152,7 +149,6 @@
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
| OPTION_MASK_TOC_FUSION \
| OPTION_MASK_VSX \
- | OPTION_MASK_VSX_SMALL_INTEGER \
| OPTION_MASK_VSX_TIMODE)
#endif
===================================================================
@@ -2104,14 +2104,11 @@ rs6000_hard_regno_mode_ok (int regno, ma
if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
return 1;
- if (TARGET_VSX_SMALL_INTEGER)
- {
- if (mode == SImode)
- return 1;
+ if (TARGET_P8_VECTOR && (mode == SImode))
+ return 1;
- if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
- return 1;
- }
+ if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
+ return 1;
}
if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
@@ -3291,7 +3288,7 @@ rs6000_init_hard_regno_mode_ok (bool glo
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
/* Support small integers in VSX registers. */
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
{
rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
@@ -3446,18 +3443,14 @@ rs6000_init_hard_regno_mode_ok (bool glo
}
}
- if (TARGET_VSX)
- {
- reg_addr[DFmode].scalar_in_vmx_p = true;
- reg_addr[DImode].scalar_in_vmx_p = true;
- }
+ reg_addr[DFmode].scalar_in_vmx_p = true;
+ reg_addr[DImode].scalar_in_vmx_p = true;
if (TARGET_P8_VECTOR)
- reg_addr[SFmode].scalar_in_vmx_p = true;
-
- if (TARGET_VSX_SMALL_INTEGER)
{
+ reg_addr[SFmode].scalar_in_vmx_p = true;
reg_addr[SImode].scalar_in_vmx_p = true;
+
if (TARGET_P9_VECTOR)
{
reg_addr[HImode].scalar_in_vmx_p = true;
@@ -4632,20 +4625,6 @@ rs6000_option_override_internal (bool gl
}
}
- /* Check whether we should allow small integers into VSX registers. We
- require direct move to prevent the register allocator from having to move
- variables through memory to do moves. SImode can be used on ISA 2.07,
- while HImode and QImode require ISA 3.0. */
- if (TARGET_VSX_SMALL_INTEGER
- && (!TARGET_DIRECT_MOVE || !TARGET_P8_VECTOR))
- {
- if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_SMALL_INTEGER)
- error ("-mvsx-small-integer requires -mpower8-vector, "
- "and -mdirect-move");
-
- rs6000_isa_flags &= ~OPTION_MASK_VSX_SMALL_INTEGER;
- }
-
/* Set long double size before the IEEE 128-bit tests. */
if (!global_options_set.x_rs6000_long_double_type_size)
{
@@ -7338,7 +7317,7 @@ rs6000_expand_vector_set (rtx target, rt
else if (mode == V2DImode)
insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
- else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64)
+ else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
{
if (mode == V4SImode)
insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
@@ -19713,7 +19692,7 @@ rs6000_secondary_reload_simple_move (enu
}
/* ISA 2.07: MTVSRWZ or MFVSRWZ. */
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
{
if (mode == SImode)
return true;
@@ -20547,7 +20526,6 @@ rs6000_preferred_reload_class (rtx x, en
/* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
a sign extend in the Altivec registers. */
if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
- && TARGET_VSX_SMALL_INTEGER
&& (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
return ALTIVEC_REGS;
}
@@ -36255,7 +36233,6 @@ static struct rs6000_opt_mask const rs60
{ "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
- { "vsx-small-integer", OPTION_MASK_VSX_SMALL_INTEGER, false, true },
{ "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
#ifdef OPTION_MASK_64BIT
#if TARGET_AIX_OS
===================================================================
@@ -1004,8 +1004,7 @@ (define_insn "extendsi<mode>2"
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")
(sign_extend:DI (match_operand:SI 1 "altivec_register_operand")))]
- "TARGET_VSX_SMALL_INTEGER && TARGET_P8_VECTOR && !TARGET_P9_VECTOR
- && reload_completed"
+ "TARGET_P8_VECTOR && !TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx dest = operands[0];
@@ -5161,7 +5160,7 @@ (define_insn_and_split "floatsi<mode>2_l
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (DImode);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_insn (gen_extendsidi2 (operands[2], operands[1]));
else
emit_insn (gen_lfiwax (operands[2], operands[1]));
@@ -5238,7 +5237,7 @@ (define_insn_and_split "floatunssi<mode>
operands[1] = rs6000_address_for_fpconvert (operands[1]);
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (DImode);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_insn (gen_zero_extendsidi2 (operands[2], operands[1]));
else
emit_insn (gen_lfiwzx (operands[2], operands[1]));
@@ -5423,8 +5422,7 @@ (define_expand "float<QHI:mode><FP_ISA3:
(clobber (match_scratch:DI 2))
(clobber (match_scratch:DI 3))
(clobber (match_scratch:<QHI:MODE> 4))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
{
if (MEM_P (operands[1]))
operands[1] = rs6000_address_for_fpconvert (operands[1]);
@@ -5437,8 +5435,7 @@ (define_insn_and_split "*float<QHI:mode>
(clobber (match_scratch:DI 2 "=wK,wi,wK"))
(clobber (match_scratch:DI 3 "=X,r,X"))
(clobber (match_scratch:<QHI:MODE> 4 "=X,X,wK"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5477,8 +5474,7 @@ (define_expand "floatuns<QHI:mode><FP_IS
(match_operand:QHI 1 "input_operand" "")))
(clobber (match_scratch:DI 2 ""))
(clobber (match_scratch:DI 3 ""))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
{
if (MEM_P (operands[1]))
operands[1] = rs6000_address_for_fpconvert (operands[1]);
@@ -5490,8 +5486,7 @@ (define_insn_and_split "*floatuns<QHI:mo
(match_operand:QHI 1 "reg_or_indexed_operand" "wK,r,Z")))
(clobber (match_scratch:DI 2 "=wK,wi,wJwK"))
(clobber (match_scratch:DI 3 "=X,r,X"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5524,7 +5519,7 @@ (define_expand "fix_trunc<mode>si2"
"TARGET_HARD_FLOAT && <TARGET_FLOAT>"
"
{
- if (!TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_P8_VECTOR)
{
rtx src = force_reg (<MODE>mode, operands[1]);
@@ -5551,7 +5546,7 @@ (define_insn_and_split "fix_trunc<mode>s
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
&& TARGET_STFIWX && can_create_pseudo_p ()
- && !TARGET_VSX_SMALL_INTEGER"
+ && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5592,7 +5587,7 @@ (define_insn_and_split "fix_trunc<mode>s
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5629,8 +5624,7 @@ (define_expand "fix_trunc<SFDF:mode><QHI
[(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
(fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
(clobber (match_scratch:DI 2))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
{
if (MEM_P (operands[0]))
operands[0] = rs6000_address_for_fpconvert (operands[0]);
@@ -5641,8 +5635,7 @@ (define_insn_and_split "*fix_trunc<SFDF:
(fix:QHI
(match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
(clobber (match_scratch:DI 2 "=X,wi"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5672,7 +5665,7 @@ (define_expand "fixuns_trunc<mode>si2"
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX"
"
{
- if (!TARGET_VSX_SMALL_INTEGER)
+ if (!TARGET_P8_VECTOR)
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
@@ -5685,7 +5678,7 @@ (define_insn_and_split "fixuns_trunc<mod
(clobber (match_scratch:DI 2 "=d"))]
"TARGET_HARD_FLOAT && <TARGET_FLOAT> && TARGET_FCTIWUZ
&& TARGET_STFIWX && can_create_pseudo_p ()
- && !TARGET_VSX_SMALL_INTEGER"
+ && !TARGET_P8_VECTOR"
"#"
""
[(pc)]
@@ -5734,8 +5727,7 @@ (define_expand "fixuns_trunc<SFDF:mode><
[(parallel [(set (match_operand:<QHI:MODE> 0 "nonimmediate_operand")
(unsigned_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand")))
(clobber (match_scratch:DI 2))])]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
{
if (MEM_P (operands[0]))
operands[0] = rs6000_address_for_fpconvert (operands[0]);
@@ -5746,8 +5738,7 @@ (define_insn_and_split "*fixuns_trunc<SF
(unsigned_fix:QHI
(match_operand:SFDF 1 "gpc_reg_operand" "<SFDF:Fv>,<SFDF:Fv>")))
(clobber (match_scratch:DI 2 "=X,wi"))]
- "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT
- && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -5777,7 +5768,7 @@ (define_insn_and_split "*fixuns_trunc<SF
(define_insn "*fctiw<u>z_<mode>_smallint"
[(set (match_operand:SI 0 "vsx_register_operand" "=d,wi")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
"@
fctiw<u>z %0,%1
xscvdp<su>xws %x0,%x1"
@@ -5789,7 +5780,7 @@ (define_insn_and_split "*fctiw<u>z_<mode
[(set (match_operand:SI 0 "memory_operand" "=Z")
(any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa")))
(clobber (match_scratch:SI 2 "=wa"))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_VSX_SMALL_INTEGER"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR"
"#"
"&& reload_completed"
[(set (match_dup 2)
@@ -6959,7 +6950,7 @@ (define_split
(define_split
[(set (match_operand:DI 0 "altivec_register_operand")
(match_operand:DI 1 "xxspltib_constant_split"))]
- "TARGET_VSX_SMALL_INTEGER && TARGET_P9_VECTOR && reload_completed"
+ "TARGET_P9_VECTOR && reload_completed"
[(const_int 0)]
{
rtx op0 = operands[0];
===================================================================
@@ -606,10 +606,6 @@ mfloat128-convert
Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
Enable default conversions between __float128 & long double.
-mvsx-small-integer
-Target Report Mask(VSX_SMALL_INTEGER) Var(rs6000_isa_flags)
-Enable small integers to be in VSX registers.
-
mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
Use given stack-protector guard.
===================================================================
@@ -2938,7 +2938,7 @@ (define_expand "vsx_extract_<mode>"
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
{
/* If we have ISA 3.0, we can do a xxextractuw/vextractu{b,h}. */
- if (TARGET_VSX_SMALL_INTEGER && TARGET_P9_VECTOR)
+ if (TARGET_P9_VECTOR)
{
emit_insn (gen_vsx_extract_<mode>_p9 (operands[0], operands[1],
operands[2]));
@@ -2952,8 +2952,7 @@ (define_insn "vsx_extract_<mode>_p9"
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n,n")])))
(clobber (match_scratch:SI 3 "=r,X"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
{
if (which_alternative == 0)
return "#";
@@ -2983,8 +2982,7 @@ (define_split
(match_operand:VSX_EXTRACT_I 1 "altivec_register_operand")
(parallel [(match_operand:QI 2 "const_int_operand")])))
(clobber (match_operand:SI 3 "int_reg_operand"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER && reload_completed"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB && reload_completed"
[(const_int 0)]
{
rtx op0_si = gen_rtx_REG (SImode, REGNO (operands[0]));
@@ -3009,8 +3007,7 @@ (define_insn_and_split "*vsx_extract_<mo
(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "wK,<VSX_EX>")
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
(clobber (match_scratch:SI 3 "=r,X"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 4)
@@ -3030,8 +3027,7 @@ (define_insn_and_split "*vsx_extract_<mo
(parallel [(match_operand:QI 2 "const_int_operand" "n,n")])))
(clobber (match_scratch:<VS_scalar> 3 "=<VSX_EX>,&r"))
(clobber (match_scratch:SI 4 "=X,&r"))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB
- && TARGET_VSX_SMALL_INTEGER"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_VEXTRACTUB"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3048,8 +3044,7 @@ (define_insn_and_split "*vsx_extract_si
(match_operand:V4SI 1 "gpc_reg_operand" "wJv,wJv,wJv")
(parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")])))
(clobber (match_scratch:V4SI 3 "=wJv,wJv,wJv"))]
- "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT
- && (!TARGET_P9_VECTOR || !TARGET_VSX_SMALL_INTEGER)"
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT && !TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -3067,15 +3062,7 @@ (define_insn_and_split "*vsx_extract_si
instruction. */
value = INTVAL (element);
if (value != 1)
- {
- if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER)
- {
- rtx si_tmp = gen_rtx_REG (SImode, REGNO (vec_tmp));
- emit_insn (gen_vsx_extract_v4si_p9 (si_tmp,src, element));
- }
- else
- emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element));
- }
+ emit_insn (gen_altivec_vspltw_direct (vec_tmp, src, element));
else
vec_tmp = src;
@@ -3084,13 +3071,13 @@ (define_insn_and_split "*vsx_extract_si
if (can_create_pseudo_p ())
dest = rs6000_address_for_fpconvert (dest);
- if (TARGET_VSX_SMALL_INTEGER)
+ if (TARGET_P8_VECTOR)
emit_move_insn (dest, gen_rtx_REG (SImode, REGNO (vec_tmp)));
else
emit_insn (gen_stfiwx (dest, gen_rtx_REG (DImode, REGNO (vec_tmp))));
}
- else if (TARGET_VSX_SMALL_INTEGER)
+ else if (TARGET_P8_VECTOR)
emit_move_insn (dest, gen_rtx_REG (SImode, REGNO (vec_tmp)));
else
emit_move_insn (gen_rtx_REG (DImode, REGNO (dest)),
@@ -3108,7 +3095,7 @@ (define_insn_and_split "*vsx_extract_<m
(parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
(clobber (match_scratch:VSX_EXTRACT_I2 3 "=v"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && (!TARGET_P9_VECTOR || !TARGET_VSX_SMALL_INTEGER)"
+ && !TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(const_int 0)]
@@ -3319,7 +3306,7 @@ (define_insn_and_split "*vsx_ext_<VSX_EX
(parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
(clobber (match_scratch:<VSX_EXTRACT_I:VS_scalar> 3 "=v"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3343,7 +3330,7 @@ (define_insn_and_split "*vsx_ext_<VSX_EX
(parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
(clobber (match_scratch:<VSX_EXTRACT_I:VS_scalar> 3 "=v"))]
"VECTOR_MEM_VSX_P (<VSX_EXTRACT_I:MODE>mode) && TARGET_DIRECT_MOVE_64BIT
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER"
+ && TARGET_P9_VECTOR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 3)
@@ -3365,8 +3352,7 @@ (define_insn "vsx_set_<mode>_p9"
(match_operand:<VS_scalar> 2 "gpc_reg_operand" "<VSX_EX>")
(match_operand:QI 3 "<VSX_EXTRACT_PREDICATE>" "n")]
UNSPEC_VSX_SET))]
- "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
{
int ele = INTVAL (operands[3]);
int nunits = GET_MODE_NUNITS (<MODE>mode);
@@ -3390,8 +3376,7 @@ (define_insn_and_split "vsx_set_v4sf_p9"
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 5)
@@ -3426,8 +3411,7 @@ (define_insn_and_split "*vsx_set_v4sf_p9
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wJwK"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64"
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64"
"#"
"&& reload_completed"
[(set (match_dup 4)
@@ -3457,8 +3441,7 @@ (define_insn "*vsx_insert_extract_v4sf_p
[(match_operand:QI 3 "const_0_to_3_operand" "n")]))
(match_operand:QI 4 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
- && TARGET_POWERPC64
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_POWERPC64
&& (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
{
int ele = INTVAL (operands[4]);
@@ -3486,7 +3469,7 @@ (define_insn_and_split "*vsx_insert_extr
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 5 "=&wJwK"))]
"VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
- && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER && TARGET_POWERPC64
+ && TARGET_P9_VECTOR && TARGET_POWERPC64
&& (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
"#"
"&& 1"
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_d_constraint (short *p)
{
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
unsigned int foo (unsigned short u)
{
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_v_constraint (short *p)
{
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_d_constraint (signed char *p)
{
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
unsigned int foo (unsigned char u)
{
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-options "-mcpu=power9 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power9 -O2" } */
double load_asm_v_constraint (signed char *p)
{
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
double load_asm_d_constraint (int *p)
{
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
unsigned int foo (unsigned int u)
{
===================================================================
@@ -2,7 +2,7 @@
/* { dg-skip-if "" { powerpc*-*-darwin* } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
-/* { dg-options "-mcpu=power8 -O2 -mvsx-small-integer" } */
+/* { dg-options "-mcpu=power8 -O2" } */
double load_asm_v_constraint (int *p)
{