[03/14] clk: tegra: disable SSC for PLL_D2

Submitted by Peter De Schrijver on July 25, 2017, 10:34 a.m.

Details

Message ID 1500978856-5981-4-git-send-email-pdeschrijver@nvidia.com
State New
Headers show

Commit Message

Peter De Schrijver July 25, 2017, 10:34 a.m.
PLLD2 is used for HDMI which does not allowe Spread Spectrum clocking.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-tegra210.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 1024e85..facd6ee 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -146,7 +146,7 @@ 
 #define PLLD_SDM_EN_MASK BIT(16)
 
 #define PLLD2_SDM_EN_MASK BIT(31)
-#define PLLD2_SSC_EN_MASK BIT(30)
+#define PLLD2_SSC_EN_MASK 0
 
 #define PLLDP_SS_CFG	0x598
 #define PLLDP_SDM_EN_MASK BIT(31)