Message ID | 20170725085036.GO2123@tucnak |
---|---|
State | New |
Headers | show |
On Tue, Jul 25, 2017 at 10:50 AM, Jakub Jelinek <jakub@redhat.com> wrote: > Hi! > > As mentioned in the PR, the following testcases ICE if AVX512BW/VL is enabled, > but AVX512DQ is not. The problem is that for movti_internal we need to use > vpextrq or vpinsrq instructions to extract or insert the 64-bit reg from > above the lowest 64-bit and if it is in %xmm16+ register, we need EVEX > encoded insn to do that. Only vpextr[bw] and vpinsr[bw] are in AVX512BW, > the rest is AVX512DQ. > > Yd/Ye constraints are only used in movdi_internal and movti_internal > patterns, in the former only for !TARGET_64BIT (then ALL_SSE_REGS vs. > SSE_REGS makes no difference), in the latter is this case I'm trying to fix. > > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? > > 2017-07-25 Jakub Jelinek <jakub@redhat.com> > > PR target/81532 > * config/i386/constraints.md (Yd, Ye): Use ALL_SSE_REGS for > TARGET_AVX512DQ rather than TARGET_AVX512BW. > > * gcc.target/i386/pr80833-3.c: New test. > * gcc.target/i386/avx512dq-pr81532.c: New test. > * gcc.target/i386/avx512bw-pr81532.c: New test. OK. Thanks, Uros. > --- gcc/config/i386/constraints.md.jj 2017-06-02 09:01:21.000000000 +0200 > +++ gcc/config/i386/constraints.md 2017-07-24 12:58:06.778105305 +0200 > @@ -138,19 +138,19 @@ (define_register_constraint "Yj" > > (define_register_constraint "Yd" > "TARGET_INTER_UNIT_MOVES_TO_VEC > - ? (TARGET_AVX512BW > + ? (TARGET_AVX512DQ > ? ALL_SSE_REGS > : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) > : NO_REGS" > - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") > + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") > > (define_register_constraint "Ye" > "TARGET_INTER_UNIT_MOVES_FROM_VEC > - ? (TARGET_AVX512BW > + ? (TARGET_AVX512DQ > ? ALL_SSE_REGS > : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) > : NO_REGS" > - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") > + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") > > (define_register_constraint "Ym" > "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" > --- gcc/testsuite/gcc.target/i386/pr80833-3.c.jj 2017-07-24 13:20:00.061347826 +0200 > +++ gcc/testsuite/gcc.target/i386/pr80833-3.c 2017-07-24 13:23:17.711976351 +0200 > @@ -0,0 +1,14 @@ > +/* { dg-do compile { target int128 } } */ > +/* { dg-options "-O2 -mavx512dq -mavx512vl -mno-avx512bw -mtune=intel" } */ > + > +__int128 test (__int128 a) > +{ > + asm ("" : "+v" (a) : : "xmm0", "xmm1", "xmm2", "xmm3", > + "xmm4", "xmm5", "xmm6", "xmm7", > + "xmm8", "xmm9", "xmm10", "xmm11", > + "xmm12", "xmm13", "xmm14", "xmm15"); > + return a; > +} > + > +/* { dg-final { scan-assembler "pinsrq" } } */ > +/* { dg-final { scan-assembler "pextrq" } } */ > --- gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c.jj 2017-07-24 13:12:09.165997780 +0200 > +++ gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c 2017-07-24 13:13:59.950668550 +0200 > @@ -0,0 +1,12 @@ > +/* PR target/81532 */ > +/* { dg-do compile { target int128 } } */ > +/* { dg-options "-O2 -mavx512dq -mavx512vl -mno-avx512bw" } */ > + > +typedef unsigned __int128 V __attribute__ ((vector_size (64))); > + > +V > +foo (V c) > +{ > + c >>= 0 != c; > + return c; > +} > --- gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c.jj 2017-07-24 13:12:40.660619897 +0200 > +++ gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c 2017-07-24 13:14:20.984416180 +0200 > @@ -0,0 +1,5 @@ > +/* PR target/81532 */ > +/* { dg-do compile { target int128 } } */ > +/* { dg-options "-O2 -mavx512bw -mavx512vl -mno-avx512dq" } */ > + > +#include "avx512dq-pr81532.c" > > Jakub
--- gcc/config/i386/constraints.md.jj 2017-06-02 09:01:21.000000000 +0200 +++ gcc/config/i386/constraints.md 2017-07-24 12:58:06.778105305 +0200 @@ -138,19 +138,19 @@ (define_register_constraint "Yj" (define_register_constraint "Yd" "TARGET_INTER_UNIT_MOVES_TO_VEC - ? (TARGET_AVX512BW + ? (TARGET_AVX512DQ ? ALL_SSE_REGS : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") (define_register_constraint "Ye" "TARGET_INTER_UNIT_MOVES_FROM_VEC - ? (TARGET_AVX512BW + ? (TARGET_AVX512DQ ? ALL_SSE_REGS : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") (define_register_constraint "Ym" "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" --- gcc/testsuite/gcc.target/i386/pr80833-3.c.jj 2017-07-24 13:20:00.061347826 +0200 +++ gcc/testsuite/gcc.target/i386/pr80833-3.c 2017-07-24 13:23:17.711976351 +0200 @@ -0,0 +1,14 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512dq -mavx512vl -mno-avx512bw -mtune=intel" } */ + +__int128 test (__int128 a) +{ + asm ("" : "+v" (a) : : "xmm0", "xmm1", "xmm2", "xmm3", + "xmm4", "xmm5", "xmm6", "xmm7", + "xmm8", "xmm9", "xmm10", "xmm11", + "xmm12", "xmm13", "xmm14", "xmm15"); + return a; +} + +/* { dg-final { scan-assembler "pinsrq" } } */ +/* { dg-final { scan-assembler "pextrq" } } */ --- gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c.jj 2017-07-24 13:12:09.165997780 +0200 +++ gcc/testsuite/gcc.target/i386/avx512dq-pr81532.c 2017-07-24 13:13:59.950668550 +0200 @@ -0,0 +1,12 @@ +/* PR target/81532 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512dq -mavx512vl -mno-avx512bw" } */ + +typedef unsigned __int128 V __attribute__ ((vector_size (64))); + +V +foo (V c) +{ + c >>= 0 != c; + return c; +} --- gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c.jj 2017-07-24 13:12:40.660619897 +0200 +++ gcc/testsuite/gcc.target/i386/avx512bw-pr81532.c 2017-07-24 13:14:20.984416180 +0200 @@ -0,0 +1,5 @@ +/* PR target/81532 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mavx512bw -mavx512vl -mno-avx512dq" } */ + +#include "avx512dq-pr81532.c"