[09/10] acpi: spcr: add SBBR compliance tests

Message ID 1500963057-4225-10-git-send-email-Sakar.Arora@arm.com
State Accepted
Headers show

Commit Message

Sakar Arora July 25, 2017, 6:10 a.m.
From: Mahesh Bireddy <mahesh.reddybireddy@arm.com>

Server Base Boot Requirements (SBBR) specification is intended for SBSA-
compliant 64-bit ARMv8 servers. It defines the base firmware
requirements for out-of-box support of any ARM SBSA-compatible
Operating System or hypervisor. The requirements in this specification
are expected to be minimal yet complete for booting a multi-core ARMv8
server platform, while leaving plenty of room for OEM or ODM innovations
and design details. For more information, download the SBBR
specification here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0044b/index.html

This change introduces test cases as per SBBR specification to spcr acpi table.
It adds additional tests including revision check and GSIV check tests.

Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
Signed-off-by: Mahesh Bireddy <mahesh.reddybireddy@arm.com>
---
 src/acpi/spcr/spcr.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 42 insertions(+), 3 deletions(-)

Comments

Alex Hung Aug. 4, 2017, 1:01 a.m. | #1
On 2017-07-24 11:10 PM, Sakar Arora wrote:
> From: Mahesh Bireddy <mahesh.reddybireddy@arm.com>
> 
> Server Base Boot Requirements (SBBR) specification is intended for SBSA-
> compliant 64-bit ARMv8 servers. It defines the base firmware
> requirements for out-of-box support of any ARM SBSA-compatible
> Operating System or hypervisor. The requirements in this specification
> are expected to be minimal yet complete for booting a multi-core ARMv8
> server platform, while leaving plenty of room for OEM or ODM innovations
> and design details. For more information, download the SBBR
> specification here:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0044b/index.html
> 
> This change introduces test cases as per SBBR specification to spcr acpi table.
> It adds additional tests including revision check and GSIV check tests.
> 
> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
> Signed-off-by: Mahesh Bireddy <mahesh.reddybireddy@arm.com>
> ---
>   src/acpi/spcr/spcr.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 42 insertions(+), 3 deletions(-)
> 
> diff --git a/src/acpi/spcr/spcr.c b/src/acpi/spcr/spcr.c
> index c38229b..2660879 100644
> --- a/src/acpi/spcr/spcr.c
> +++ b/src/acpi/spcr/spcr.c
> @@ -39,8 +39,13 @@ static int spcr_init(fwts_framework *fw)
>   		return FWTS_ERROR;
>   	}
>   	if (table == NULL || (table && table->length == 0)) {
> -		fwts_log_error(fw, "ACPI SPCR table does not exist, skipping test");
> -		return FWTS_SKIP;
> +		if (fw->flags & FWTS_FLAG_TEST_SBBR) {
> +			fwts_log_error(fw, "ACPI SPCR table does not exist");
> +			return FWTS_ERROR;
> +		} else {
> +			fwts_log_error(fw, "ACPI SPCR table does not exist, skipping test");
> +			return FWTS_SKIP;
> +		}
>   	}
>   	spcr = (const fwts_acpi_table_spcr*)table->data;
>   
> @@ -52,6 +57,38 @@ static int spcr_init(fwts_framework *fw)
>    *	https://msdn.microsoft.com/en-gb/library/windows/hardware/dn639132%28v=vs.85%29.aspx
>    *	https://msdn.microsoft.com/en-us/library/windows/hardware/dn639131%28v=vs.85%29.aspx
>    */
> +static int spcr_sbbr_revision_test(fwts_framework *fw)
> +{
> +	if (fw->flags & FWTS_FLAG_TEST_SBBR) {
> +		const uint8_t SBBR_LATEST_REVISION = 2;
> +
> +		if (spcr->header.revision >= SBBR_LATEST_REVISION)
> +			fwts_passed(fw, "SPCR revision is up to date.");
> +		else
> +			fwts_failed(fw, LOG_LEVEL_CRITICAL, "spcr_revision:", "SPCR revision is outdated: %d",
> +					spcr->header.revision);
> +
> +	}
> +
> +	return FWTS_OK;
> +}
> +
> +static int spcr_sbbr_gsiv_test(fwts_framework *fw)
> +{
> +	if (fw->flags & FWTS_FLAG_TEST_SBBR) {
> +		const uint8_t ARMH_GIC_INTR_MASK = 0x08;
> +
> +		if ( (spcr->interrupt_type == ARMH_GIC_INTR_MASK) &&
> +		     (spcr->gsi            != 0x0000000000000000)    )
> +			fwts_passed(fw, "SPCR appears to be populated with correct GSIV interrupt"
> +						"routing information for ARM PL011 UART Device");
> +		else
> +			fwts_failed(fw, LOG_LEVEL_CRITICAL, "sbbr_gsiv:", "SPCR GSIV Information is set incorrectly.");
> +	}
> +
> +	return FWTS_OK;
> +}
> +
>   static int spcr_test1(fwts_framework *fw)
>   {
>   	char *str;
> @@ -296,6 +333,8 @@ static int spcr_test1(fwts_framework *fw)
>   
>   static fwts_framework_minor_test spcr_tests[] = {
>   	{ spcr_test1, "SPCR Serial Port Console Redirection Table test." },
> +	{ spcr_sbbr_revision_test, "SPCR Revision Test." },
> +	{ spcr_sbbr_gsiv_test, "SPCR GSIV Interrupt Test." },
>   	{ NULL, NULL }
>   };
>   
> @@ -305,6 +344,6 @@ static fwts_framework_ops spcr_ops = {
>   	.minor_tests = spcr_tests
>   };
>   
> -FWTS_REGISTER("spcr", &spcr_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI)
> +FWTS_REGISTER("spcr", &spcr_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI | FWTS_FLAG_TEST_SBBR)
>   
>   #endif
> 

Acked-by: Alex Hung <alex.hung@canonical.com>
Colin King Aug. 22, 2017, 4:44 p.m. | #2
On 25/07/17 07:10, Sakar Arora wrote:
> From: Mahesh Bireddy <mahesh.reddybireddy@arm.com>
> 
> Server Base Boot Requirements (SBBR) specification is intended for SBSA-
> compliant 64-bit ARMv8 servers. It defines the base firmware
> requirements for out-of-box support of any ARM SBSA-compatible
> Operating System or hypervisor. The requirements in this specification
> are expected to be minimal yet complete for booting a multi-core ARMv8
> server platform, while leaving plenty of room for OEM or ODM innovations
> and design details. For more information, download the SBBR
> specification here:
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0044b/index.html
> 
> This change introduces test cases as per SBBR specification to spcr acpi table.
> It adds additional tests including revision check and GSIV check tests.
> 
> Signed-off-by: Supreeth Venkatesh <supreeth.venkatesh@arm.com>
> Signed-off-by: Mahesh Bireddy <mahesh.reddybireddy@arm.com>
> ---
>  src/acpi/spcr/spcr.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
>  1 file changed, 42 insertions(+), 3 deletions(-)
> 
> diff --git a/src/acpi/spcr/spcr.c b/src/acpi/spcr/spcr.c
> index c38229b..2660879 100644
> --- a/src/acpi/spcr/spcr.c
> +++ b/src/acpi/spcr/spcr.c
> @@ -39,8 +39,13 @@ static int spcr_init(fwts_framework *fw)
>  		return FWTS_ERROR;
>  	}
>  	if (table == NULL || (table && table->length == 0)) {
> -		fwts_log_error(fw, "ACPI SPCR table does not exist, skipping test");
> -		return FWTS_SKIP;
> +		if (fw->flags & FWTS_FLAG_TEST_SBBR) {
> +			fwts_log_error(fw, "ACPI SPCR table does not exist");
> +			return FWTS_ERROR;
> +		} else {
> +			fwts_log_error(fw, "ACPI SPCR table does not exist, skipping test");
> +			return FWTS_SKIP;
> +		}
>  	}
>  	spcr = (const fwts_acpi_table_spcr*)table->data;
>  
> @@ -52,6 +57,38 @@ static int spcr_init(fwts_framework *fw)
>   *	https://msdn.microsoft.com/en-gb/library/windows/hardware/dn639132%28v=vs.85%29.aspx
>   *	https://msdn.microsoft.com/en-us/library/windows/hardware/dn639131%28v=vs.85%29.aspx
>   */
> +static int spcr_sbbr_revision_test(fwts_framework *fw)
> +{
> +	if (fw->flags & FWTS_FLAG_TEST_SBBR) {
> +		const uint8_t SBBR_LATEST_REVISION = 2;
> +
> +		if (spcr->header.revision >= SBBR_LATEST_REVISION)
> +			fwts_passed(fw, "SPCR revision is up to date.");
> +		else
> +			fwts_failed(fw, LOG_LEVEL_CRITICAL, "spcr_revision:", "SPCR revision is outdated: %d",
> +					spcr->header.revision);
> +
> +	}
> +
> +	return FWTS_OK;
> +}
> +
> +static int spcr_sbbr_gsiv_test(fwts_framework *fw)
> +{
> +	if (fw->flags & FWTS_FLAG_TEST_SBBR) {
> +		const uint8_t ARMH_GIC_INTR_MASK = 0x08;
> +
> +		if ( (spcr->interrupt_type == ARMH_GIC_INTR_MASK) &&
> +		     (spcr->gsi            != 0x0000000000000000)    )
> +			fwts_passed(fw, "SPCR appears to be populated with correct GSIV interrupt"
> +						"routing information for ARM PL011 UART Device");
> +		else
> +			fwts_failed(fw, LOG_LEVEL_CRITICAL, "sbbr_gsiv:", "SPCR GSIV Information is set incorrectly.");
> +	}
> +
> +	return FWTS_OK;
> +}
> +
>  static int spcr_test1(fwts_framework *fw)
>  {
>  	char *str;
> @@ -296,6 +333,8 @@ static int spcr_test1(fwts_framework *fw)
>  
>  static fwts_framework_minor_test spcr_tests[] = {
>  	{ spcr_test1, "SPCR Serial Port Console Redirection Table test." },
> +	{ spcr_sbbr_revision_test, "SPCR Revision Test." },
> +	{ spcr_sbbr_gsiv_test, "SPCR GSIV Interrupt Test." },
>  	{ NULL, NULL }
>  };
>  
> @@ -305,6 +344,6 @@ static fwts_framework_ops spcr_ops = {
>  	.minor_tests = spcr_tests
>  };
>  
> -FWTS_REGISTER("spcr", &spcr_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI)
> +FWTS_REGISTER("spcr", &spcr_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI | FWTS_FLAG_TEST_SBBR)
>  
>  #endif
> 
Acked-by: Colin Ian King <colin.king@canonical.com>

Patch

diff --git a/src/acpi/spcr/spcr.c b/src/acpi/spcr/spcr.c
index c38229b..2660879 100644
--- a/src/acpi/spcr/spcr.c
+++ b/src/acpi/spcr/spcr.c
@@ -39,8 +39,13 @@  static int spcr_init(fwts_framework *fw)
 		return FWTS_ERROR;
 	}
 	if (table == NULL || (table && table->length == 0)) {
-		fwts_log_error(fw, "ACPI SPCR table does not exist, skipping test");
-		return FWTS_SKIP;
+		if (fw->flags & FWTS_FLAG_TEST_SBBR) {
+			fwts_log_error(fw, "ACPI SPCR table does not exist");
+			return FWTS_ERROR;
+		} else {
+			fwts_log_error(fw, "ACPI SPCR table does not exist, skipping test");
+			return FWTS_SKIP;
+		}
 	}
 	spcr = (const fwts_acpi_table_spcr*)table->data;
 
@@ -52,6 +57,38 @@  static int spcr_init(fwts_framework *fw)
  *	https://msdn.microsoft.com/en-gb/library/windows/hardware/dn639132%28v=vs.85%29.aspx
  *	https://msdn.microsoft.com/en-us/library/windows/hardware/dn639131%28v=vs.85%29.aspx
  */
+static int spcr_sbbr_revision_test(fwts_framework *fw)
+{
+	if (fw->flags & FWTS_FLAG_TEST_SBBR) {
+		const uint8_t SBBR_LATEST_REVISION = 2;
+
+		if (spcr->header.revision >= SBBR_LATEST_REVISION)
+			fwts_passed(fw, "SPCR revision is up to date.");
+		else
+			fwts_failed(fw, LOG_LEVEL_CRITICAL, "spcr_revision:", "SPCR revision is outdated: %d",
+					spcr->header.revision);
+
+	}
+
+	return FWTS_OK;
+}
+
+static int spcr_sbbr_gsiv_test(fwts_framework *fw)
+{
+	if (fw->flags & FWTS_FLAG_TEST_SBBR) {
+		const uint8_t ARMH_GIC_INTR_MASK = 0x08;
+
+		if ( (spcr->interrupt_type == ARMH_GIC_INTR_MASK) &&
+		     (spcr->gsi            != 0x0000000000000000)    )
+			fwts_passed(fw, "SPCR appears to be populated with correct GSIV interrupt"
+						"routing information for ARM PL011 UART Device");
+		else
+			fwts_failed(fw, LOG_LEVEL_CRITICAL, "sbbr_gsiv:", "SPCR GSIV Information is set incorrectly.");
+	}
+
+	return FWTS_OK;
+}
+
 static int spcr_test1(fwts_framework *fw)
 {
 	char *str;
@@ -296,6 +333,8 @@  static int spcr_test1(fwts_framework *fw)
 
 static fwts_framework_minor_test spcr_tests[] = {
 	{ spcr_test1, "SPCR Serial Port Console Redirection Table test." },
+	{ spcr_sbbr_revision_test, "SPCR Revision Test." },
+	{ spcr_sbbr_gsiv_test, "SPCR GSIV Interrupt Test." },
 	{ NULL, NULL }
 };
 
@@ -305,6 +344,6 @@  static fwts_framework_ops spcr_ops = {
 	.minor_tests = spcr_tests
 };
 
-FWTS_REGISTER("spcr", &spcr_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI)
+FWTS_REGISTER("spcr", &spcr_ops, FWTS_TEST_ANYTIME, FWTS_FLAG_BATCH | FWTS_FLAG_TEST_ACPI | FWTS_FLAG_TEST_SBBR)
 
 #endif