From patchwork Tue Jan 18 11:22:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Babic X-Patchwork-Id: 79289 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 09E47B70EA for ; Tue, 18 Jan 2011 22:22:55 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6193A280A1; Tue, 18 Jan 2011 12:22:53 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 49uueueBxOv7; Tue, 18 Jan 2011 12:22:53 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1BA402809C; Tue, 18 Jan 2011 12:22:51 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 16B132809C for ; Tue, 18 Jan 2011 12:22:49 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id p-r2wgTU2pS4 for ; Tue, 18 Jan 2011 12:22:47 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtpi3.ngi.it (smtpi3.ngi.it [88.149.128.33]) by theia.denx.de (Postfix) with ESMTP id 06C8228099 for ; Tue, 18 Jan 2011 12:22:44 +0100 (CET) Received: from paperina.lan (unknown [88.149.182.160]) by smtpi3.ngi.it (Postfix) with ESMTP id 60536318C8D; Tue, 18 Jan 2011 12:22:44 +0100 (CET) Received: from papero.lan (papero.lan [192.168.2.245]) by paperina.lan (Postfix) with ESMTP id 06D7A140A17B; Tue, 18 Jan 2011 12:22:43 +0100 (CET) From: Stefano Babic To: u-boot@lists.denx.de Date: Tue, 18 Jan 2011 12:22:29 +0100 Message-Id: <1295349749-32406-1-git-send-email-sbabic@denx.de> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1295201837-26836-2-git-send-email-agust@denx.de> References: <1295201837-26836-2-git-send-email-agust@denx.de> Subject: [U-Boot] [PATCH V2 2/2] SPI: mxc_spi: add SPI clock calculation and setup to the driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Anatolij Gustschin The MXC SPI driver didn't calculate the SPI clock up to now and just highest possible divider 512 for DATA RATE in the control register. This results in very low transfer rates. The patch adds code to calculate and setup the SPI clock frequency for transfers. Signed-off-by: Anatolij Gustschin Signed-off-by: Stefano Babic --- Changes: The patch is rebased on the current patches already sent for this driver (support for MX35). Tested on a MX35 board. Modified commit message as suggested by Anatolij drivers/spi/mxc_spi.c | 24 +++++++++++++++++++++++- 1 files changed, 23 insertions(+), 1 deletions(-) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 0e42d41..32be7b0 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -71,6 +71,7 @@ static unsigned long spi_bases[] = { }; #define spi_cfg spi_cfg_mx3 +#define mxc_get_clock(x) mx31_get_ipg_clk() #elif defined(CONFIG_MX51) #include @@ -201,15 +202,36 @@ void spi_cs_deactivate(struct spi_slave *slave) !(mxcs->ss_pol)); } +u32 get_cspi_div(u32 div) +{ + int i; + + for (i = 0; i < 8; i++) { + if (div <= (4 << i)) + return i; + } + return i; +} + #if defined(CONFIG_MX31) || defined(CONFIG_MX35) static s32 spi_cfg_mx3(struct mxc_spi_slave *mxcs, unsigned int cs, unsigned int max_hz, unsigned int mode) { unsigned int ctrl_reg; + u32 clk_src; + u32 div; + + clk_src = mxc_get_clock(MXC_CSPI_CLK); + + div = clk_src / max_hz; + div = get_cspi_div(div); + + debug("clk %d Hz, div %d, real clk %d Hz\n", + max_hz, div, clk_src / (4 << div)); ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | - MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ + MXC_CSPICTRL_DATARATE(div) | MXC_CSPICTRL_EN | #ifdef CONFIG_MX35 MXC_CSPICTRL_SSCTL |