diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 53d918d..17dd0d2 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -277,6 +277,7 @@ int sh_eth_recv(struct eth_device *dev)
 static int sh_eth_reset(struct sh_eth_dev *eth)
 {
 	int port = eth->port;
+#if defined(CONFIG_CPU_SH7763)
 	int ret = 0, i;

 	/* Start e-dmac transmitter and receiver */
@@ -296,6 +297,13 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
 	}

 	return ret;
+#else
+	outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
+	udelay(3000);
+	outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
+
+	return 0;
+#endif
 }

 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
@@ -339,9 +347,11 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 	/* Point the controller to the tx descriptor list. Must use physical
 	   addresses */
 	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
+#if defined(CONFIG_CPU_SH7763)
 	outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
 	outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
 	outl(0x01, TDFFR(port));/* Last discriptor bit */
+#endif

 err:
 	return ret;
@@ -405,9 +415,11 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)

 	/* Point the controller to the rx descriptor list */
 	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
+#if defined(CONFIG_CPU_SH7763)
 	outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
 	outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
 	outl(RDFFR_RDLF, RDFFR(port));
+#endif

 	return ret;

@@ -532,11 +544,18 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	outl(0, TFTR(port));
 	outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
 	outl(RMCR_RST, RMCR(port));
+#ifndef CONFIG_CPU_SH7757
 	outl(0, RPADIR(port));
+#endif
 	outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));

 	/* Configure e-mac registers */
+#if defined(CONFIG_CPU_SH7757)
+	outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
+		ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
+#else
 	outl(0, ECSIPR(port));
+#endif

 	/* Set Mac address */
 	val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
@@ -547,11 +566,16 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	outl(val, MALR(port));

 	outl(RFLR_RFL_MIN, RFLR(port));
+#ifndef CONFIG_CPU_SH7757
 	outl(0, PIPR(port));
+#endif
 	outl(APR_AP, APR(port));
 	outl(MPR_MP, MPR(port));
+#ifdef CONFIG_CPU_SH7757
+	outl(TPAUSER_UNLIMITED, TPAUSER(port));
+#else
 	outl(TPAUSER_TPAUSE, TPAUSER(port));
-
+#endif
 	/* Configure phy */
 	ret = sh_eth_phy_config(eth);
 	if (ret) {
@@ -562,6 +586,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 	phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1);

 	/* Set the transfer speed */
+#ifdef CONFIG_CPU_SH7763
 	if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
 		printf(SHETHER_NAME ": 100Base/");
 		outl(GECMR_100B, GECMR(port));
@@ -569,6 +594,16 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
 		printf(SHETHER_NAME ": 10Base/");
 		outl(GECMR_10B, GECMR(port));
 	}
+#endif
+#if defined(CONFIG_CPU_SH7757)
+	if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) {
+		printf("100Base/");
+		outl(1, RTRATE(port));
+	} else {
+		printf("10Base/");
+		outl(0, RTRATE(port));
+	}
+#endif

 	/* Check if full duplex mode is supported by the phy */
 	if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index e153849..51e5d5b 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -1,5 +1,5 @@
 /*
- * sh_eth.h - Driver for Renesas SH7763's gigabit ethernet controler.
+ * sh_eth.h - Driver for Renesas SuperH ethernet controler.
  *
  * Copyright (C) 2008 Renesas Solutions Corp.
  * Copyright (c) 2008 Nobuhiro Iwamatsu
@@ -30,7 +30,11 @@
 #define ADDR_TO_P2(addr)	((((int)(addr) & ~0xe0000000) | 0xa0000000))

 /* The ethernet controller needs to use physical addresses */
+#if defined(CONFIG_SH_32BIT)
+#define ADDR_TO_PHY(addr)	((((int)(addr) & ~0xe0000000) | 0x40000000))
+#else
 #define ADDR_TO_PHY(addr)	((int)(addr) & ~0xe0000000)
+#endif

 /* Number of supported ports */
 #define MAX_PORT_NUM	2
@@ -93,6 +97,7 @@ struct sh_eth_dev {
 };

 /* Register Address */
+#ifdef CONFIG_CPU_SH7763
 #define BASE_IO_ADDR	0xfee00000

 #define EDSR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0000)
@@ -130,6 +135,34 @@ struct sh_eth_dev {
 #define MALR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
 #define MAHR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x05c0)

+#elif defined(CONFIG_CPU_SH7757)
+#define BASE_IO_ADDR	0xfef00000
+
+#define TDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0018)
+#define RDLAR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0020)
+
+#define EDMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0000)
+#define EDTRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0008)
+#define EDRRR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0010)
+#define EESR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0028)
+#define EESIPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0030)
+#define TRSCER(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0038)
+#define TFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0048)
+#define FDR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0050)
+#define RMCR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0058)
+#define FCFTR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0070)
+#define ECMR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0100)
+#define RFLR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0108)
+#define ECSIPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0118)
+#define PIR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0120)
+#define APR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0154)
+#define MPR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0158)
+#define TPAUSER(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x0164)
+#define MAHR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
+#define MALR(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
+#define RTRATE(port)		(BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
+#endif
+
 /*
  * Register's bits
  * Copy from Linux driver source code
@@ -149,6 +182,10 @@ enum DMAC_M_BIT {
 	EDMR_SRST	= 0x03,
 	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
 	EDMR_EL		= 0x40, /* Litte endian */
+#elif defined CONFIG_CPU_SH7757
+	EDMR_SRST	= 0x01,
+	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
+	EDMR_EL		= 0x40, /* Litte endian */
 #else /* CONFIG_CPU_SH7763 */
 	EDMR_SRST = 0x01,
 #endif
@@ -287,7 +324,7 @@ enum FCFTR_BIT {

 /* Transfer descriptor bit */
 enum TD_STS_BIT {
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757)
 	TD_TACT = 0x80000000,
 #else
 	TD_TACT = 0x7fffffff,
@@ -317,8 +354,10 @@ enum FELIC_MODE_BIT {
 #ifdef CONFIG_CPU_SH7763
 #define ECMR_CHG_DM	(ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
 						ECMR_TXF | ECMR_MCT)
+#elif CONFIG_CPU_SH7757
+#define ECMR_CHG_DM	(ECMR_ZPF)
 #else
-#define ECMR_CHG_DM	(ECMR_ZPF | ECMR_PFR ECMR_RXF | ECMR_TXF | ECMR_MCT)
+#define ECMR_CHG_DM	(ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
 #endif

 /* ECSR */
@@ -355,12 +394,20 @@ enum ECSIPR_STATUS_MASK_BIT {

 /* APR */
 enum APR_BIT {
+#ifdef CONFIG_CPU_SH7757
+	APR_AP = 0x00000001,
+#else
 	APR_AP = 0x00000004,
+#endif
 };

 /* MPR */
 enum MPR_BIT {
+#ifdef CONFIG_CPU_SH7757
+	MPR_MP = 0x00000001,
+#else
 	MPR_MP = 0x00000006,
+#endif
 };

 /* TRSCER */
