| Message ID | b493a0eb939fe97f7e604c0c83916e0dac1d2bce.1500879613.git.larper@axis.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Mon, Jul 24, 2017 at 09:07:29AM +0200, Lars Persson wrote: > Document the device tree bindings for the ARTPEC crypto accelerator on > ARTPEC-6 and ARTPEC-7 SoCs. > > Signed-off-by: Lars Persson <larper@axis.com> > --- > .../devicetree/bindings/crypto/artpec6-crypto.txt | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt new file mode 100644 index 000000000000..d9cca4875bd6 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/artpec6-crypto.txt @@ -0,0 +1,16 @@ +Axis crypto engine with PDMA interface. + +Required properties: +- compatible : Should be one of the following strings: + "axis,artpec6-crypto" for the version in the Axis ARTPEC-6 SoC + "axis,artpec7-crypto" for the version in the Axis ARTPEC-7 SoC. +- reg: Base address and size for the PDMA register area. +- interrupts: Interrupt handle for the PDMA interrupt line. + +Example: + +crypto@f4264000 { + compatible = "axis,artpec6-crypto"; + reg = <0xf4264000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; +};
Document the device tree bindings for the ARTPEC crypto accelerator on ARTPEC-6 and ARTPEC-7 SoCs. Signed-off-by: Lars Persson <larper@axis.com> --- .../devicetree/bindings/crypto/artpec6-crypto.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/artpec6-crypto.txt