| Message ID | 1500821077-28325-2-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Accepted |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
On 23 July 2017 at 08:44, Bin Meng <bmeng.cn@gmail.com> wrote: > On some flash (like Macronix), QE (quad enable) bit is in the same > status register as BP# bits, and we need preserve its original value > during a reboot cycle as this is required by some platforms (like > Intel ICH SPI controller working under descriptor mode). > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass <sjg@chromium.org>
On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: > On some flash (like Macronix), QE (quad enable) bit is in the same > status register as BP# bits, and we need preserve its original value > during a reboot cycle as this is required by some platforms (like > Intel ICH SPI controller working under descriptor mode). > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) > > diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c > index 0034a28..7d8c660 100644 > --- a/drivers/mtd/spi/spi_flash.c > +++ b/drivers/mtd/spi/spi_flash.c > @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) > if (IS_ERR_OR_NULL(info)) > return -ENOENT; > > - /* Flash powers up read-only, so clear BP# bits */ > + /* > + * Flash powers up read-only, so clear BP# bits. > + * > + * Note on some flash (like Macronix), QE (quad enable) bit is in the > + * same status register as BP# bits, and we need preserve its original > + * value during a reboot cycle as this is required by some platforms > + * (like Intel ICH SPI controller working under descriptor mode). > + */ > if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || > - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || > JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) > write_sr(flash, 0); > + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { > + u8 sr = 0; > + > + read_sr(flash, &sr); > + sr &= STATUS_QEB_MXIC; > + write_sr(flash, sr); > + } It doesn't make sense to have one(specific) controller fix to be generic to all macronix chips, think about alternative. thanks!
Hi Jagan, On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >> On some flash (like Macronix), QE (quad enable) bit is in the same >> status register as BP# bits, and we need preserve its original value >> during a reboot cycle as this is required by some platforms (like >> Intel ICH SPI controller working under descriptor mode). >> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >> --- >> >> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >> 1 file changed, 15 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >> index 0034a28..7d8c660 100644 >> --- a/drivers/mtd/spi/spi_flash.c >> +++ b/drivers/mtd/spi/spi_flash.c >> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >> if (IS_ERR_OR_NULL(info)) >> return -ENOENT; >> >> - /* Flash powers up read-only, so clear BP# bits */ >> + /* >> + * Flash powers up read-only, so clear BP# bits. >> + * >> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >> + * same status register as BP# bits, and we need preserve its original >> + * value during a reboot cycle as this is required by some platforms >> + * (like Intel ICH SPI controller working under descriptor mode). >> + */ >> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >> write_sr(flash, 0); >> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >> + u8 sr = 0; >> + >> + read_sr(flash, &sr); >> + sr &= STATUS_QEB_MXIC; >> + write_sr(flash, sr); >> + } > > It doesn't make sense to have one(specific) controller fix to be > generic to all macronix chips, think about alternative. > This is no way to fix at the controller level. Actually this is nothing related to controller level. It's just the bootstrap settings (QE bit in this case) that cannot be overwritten by someone else (although it's seen on Intel, it might happen on some other architecture). The logic in the codes are having issues. Its comment says: clear BP# bits, but it clears QE bit for Macronix flash as well, which is wrong. The update was just to make sure the codes do as what its comment says. If you have any other alternative, please suggest. Regards, Bin
On Wed, Aug 2, 2017 at 6:26 AM, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Jagan, > > On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> On some flash (like Macronix), QE (quad enable) bit is in the same >>> status register as BP# bits, and we need preserve its original value >>> during a reboot cycle as this is required by some platforms (like >>> Intel ICH SPI controller working under descriptor mode). >>> >>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>> --- >>> >>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>> 1 file changed, 15 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>> index 0034a28..7d8c660 100644 >>> --- a/drivers/mtd/spi/spi_flash.c >>> +++ b/drivers/mtd/spi/spi_flash.c >>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>> if (IS_ERR_OR_NULL(info)) >>> return -ENOENT; >>> >>> - /* Flash powers up read-only, so clear BP# bits */ >>> + /* >>> + * Flash powers up read-only, so clear BP# bits. >>> + * >>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>> + * same status register as BP# bits, and we need preserve its original >>> + * value during a reboot cycle as this is required by some platforms >>> + * (like Intel ICH SPI controller working under descriptor mode). >>> + */ >>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>> write_sr(flash, 0); >>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>> + u8 sr = 0; >>> + >>> + read_sr(flash, &sr); >>> + sr &= STATUS_QEB_MXIC; >>> + write_sr(flash, sr); >>> + } >> >> It doesn't make sense to have one(specific) controller fix to be >> generic to all macronix chips, think about alternative. >> > > This is no way to fix at the controller level. Actually this is > nothing related to controller level. It's just the bootstrap settings > (QE bit in this case) that cannot be overwritten by someone else > (although it's seen on Intel, it might happen on some other > architecture). The logic in the codes are having issues. Its comment > says: clear BP# bits, but it clears QE bit for Macronix flash as well, > which is wrong. The update was just to make sure the codes do as what > its comment says. > > If you have any other alternative, please suggest. > Ping again.. Can you please comment on this? I would like this patch gets in the upcoming release. Regards, Bin
On Fri, Aug 4, 2017 at 12:21 PM, Bin Meng <bmeng.cn@gmail.com> wrote: > On Wed, Aug 2, 2017 at 6:26 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi Jagan, >> >> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>> status register as BP# bits, and we need preserve its original value >>>> during a reboot cycle as this is required by some platforms (like >>>> Intel ICH SPI controller working under descriptor mode). >>>> >>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>> --- >>>> >>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>> index 0034a28..7d8c660 100644 >>>> --- a/drivers/mtd/spi/spi_flash.c >>>> +++ b/drivers/mtd/spi/spi_flash.c >>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>> if (IS_ERR_OR_NULL(info)) >>>> return -ENOENT; >>>> >>>> - /* Flash powers up read-only, so clear BP# bits */ >>>> + /* >>>> + * Flash powers up read-only, so clear BP# bits. >>>> + * >>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>> + * same status register as BP# bits, and we need preserve its original >>>> + * value during a reboot cycle as this is required by some platforms >>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>> + */ >>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>> write_sr(flash, 0); >>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>> + u8 sr = 0; >>>> + >>>> + read_sr(flash, &sr); >>>> + sr &= STATUS_QEB_MXIC; >>>> + write_sr(flash, sr); >>>> + } >>> >>> It doesn't make sense to have one(specific) controller fix to be >>> generic to all macronix chips, think about alternative. >>> >> >> This is no way to fix at the controller level. Actually this is >> nothing related to controller level. It's just the bootstrap settings >> (QE bit in this case) that cannot be overwritten by someone else >> (although it's seen on Intel, it might happen on some other >> architecture). The logic in the codes are having issues. Its comment >> says: clear BP# bits, but it clears QE bit for Macronix flash as well, >> which is wrong. The update was just to make sure the codes do as what >> its comment says. >> >> If you have any other alternative, please suggest. >> > > Ping again.. > > Can you please comment on this? I would like this patch gets in the > upcoming release. > Ping ..
Hi Bing, On Mon, Aug 7, 2017 at 1:09 PM, Bin Meng <bmeng.cn@gmail.com> wrote: > On Fri, Aug 4, 2017 at 12:21 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >> On Wed, Aug 2, 2017 at 6:26 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi Jagan, >>> >>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>> status register as BP# bits, and we need preserve its original value >>>>> during a reboot cycle as this is required by some platforms (like >>>>> Intel ICH SPI controller working under descriptor mode). >>>>> >>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>> --- >>>>> >>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>> index 0034a28..7d8c660 100644 >>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>> if (IS_ERR_OR_NULL(info)) >>>>> return -ENOENT; >>>>> >>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>> + /* >>>>> + * Flash powers up read-only, so clear BP# bits. >>>>> + * >>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>> + * same status register as BP# bits, and we need preserve its original >>>>> + * value during a reboot cycle as this is required by some platforms >>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>> + */ >>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>> write_sr(flash, 0); >>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>> + u8 sr = 0; >>>>> + >>>>> + read_sr(flash, &sr); >>>>> + sr &= STATUS_QEB_MXIC; >>>>> + write_sr(flash, sr); >>>>> + } >>>> >>>> It doesn't make sense to have one(specific) controller fix to be >>>> generic to all macronix chips, think about alternative. >>>> >>> >>> This is no way to fix at the controller level. Actually this is >>> nothing related to controller level. It's just the bootstrap settings >>> (QE bit in this case) that cannot be overwritten by someone else >>> (although it's seen on Intel, it might happen on some other >>> architecture). The logic in the codes are having issues. Its comment >>> says: clear BP# bits, but it clears QE bit for Macronix flash as well, >>> which is wrong. The update was just to make sure the codes do as what >>> its comment says. >>> >>> If you have any other alternative, please suggest. >>> >> >> Ping again.. Wait for sometime, I've queue that I need to review-it and respond accordingly patches with latest may take some time. And commenting yes will respond soon. thanks!
On Mon, Aug 7, 2017 at 3:54 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > Hi Bing, > > On Mon, Aug 7, 2017 at 1:09 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >> On Fri, Aug 4, 2017 at 12:21 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> On Wed, Aug 2, 2017 at 6:26 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>> Hi Jagan, >>>> >>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>>> status register as BP# bits, and we need preserve its original value >>>>>> during a reboot cycle as this is required by some platforms (like >>>>>> Intel ICH SPI controller working under descriptor mode). >>>>>> >>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>>> --- >>>>>> >>>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>>> >>>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>>> index 0034a28..7d8c660 100644 >>>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>>> if (IS_ERR_OR_NULL(info)) >>>>>> return -ENOENT; >>>>>> >>>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>>> + /* >>>>>> + * Flash powers up read-only, so clear BP# bits. >>>>>> + * >>>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>>> + * same status register as BP# bits, and we need preserve its original >>>>>> + * value during a reboot cycle as this is required by some platforms >>>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>>> + */ >>>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>>> write_sr(flash, 0); >>>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>>> + u8 sr = 0; >>>>>> + >>>>>> + read_sr(flash, &sr); >>>>>> + sr &= STATUS_QEB_MXIC; >>>>>> + write_sr(flash, sr); >>>>>> + } >>>>> >>>>> It doesn't make sense to have one(specific) controller fix to be >>>>> generic to all macronix chips, think about alternative. >>>>> >>>> >>>> This is no way to fix at the controller level. Actually this is >>>> nothing related to controller level. It's just the bootstrap settings >>>> (QE bit in this case) that cannot be overwritten by someone else >>>> (although it's seen on Intel, it might happen on some other >>>> architecture). The logic in the codes are having issues. Its comment >>>> says: clear BP# bits, but it clears QE bit for Macronix flash as well, >>>> which is wrong. The update was just to make sure the codes do as what >>>> its comment says. >>>> >>>> If you have any other alternative, please suggest. >>>> >>> >>> Ping again.. > > Wait for sometime, I've queue that I need to review-it and respond > accordingly patches with latest may take some time. And commenting > yes will respond soon. > Ping! Can you please respond with a reasonable time frame (ie: when you will have time to look at this)? Regards, Bin
Hi Bin, On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Jagan, > > On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> On some flash (like Macronix), QE (quad enable) bit is in the same >>> status register as BP# bits, and we need preserve its original value >>> during a reboot cycle as this is required by some platforms (like >>> Intel ICH SPI controller working under descriptor mode). >>> >>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>> --- >>> >>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>> 1 file changed, 15 insertions(+), 2 deletions(-) >>> >>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>> index 0034a28..7d8c660 100644 >>> --- a/drivers/mtd/spi/spi_flash.c >>> +++ b/drivers/mtd/spi/spi_flash.c >>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>> if (IS_ERR_OR_NULL(info)) >>> return -ENOENT; >>> >>> - /* Flash powers up read-only, so clear BP# bits */ >>> + /* >>> + * Flash powers up read-only, so clear BP# bits. >>> + * >>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>> + * same status register as BP# bits, and we need preserve its original >>> + * value during a reboot cycle as this is required by some platforms >>> + * (like Intel ICH SPI controller working under descriptor mode). >>> + */ >>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>> write_sr(flash, 0); >>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>> + u8 sr = 0; >>> + >>> + read_sr(flash, &sr); >>> + sr &= STATUS_QEB_MXIC; >>> + write_sr(flash, sr); >>> + } >> >> It doesn't make sense to have one(specific) controller fix to be >> generic to all macronix chips, think about alternative. >> > > This is no way to fix at the controller level. Actually this is > nothing related to controller level. It's just the bootstrap settings > (QE bit in this case) that cannot be overwritten by someone else > (although it's seen on Intel, it might happen on some other > architecture). The logic in the codes are having issues. Its comment > says: clear BP# bits, but it clears QE bit for Macronix flash as well, > which is wrong. The update was just to make sure the codes do as what > its comment says. I believe QEB is same position for all Macronix chips, checked few parts true? what if the supported chips from id tables doesn't have QEB at-all means specific chip support upto dual? thanks!
Hi Jagan, On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > Hi Bin, > > On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi Jagan, >> >> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>> status register as BP# bits, and we need preserve its original value >>>> during a reboot cycle as this is required by some platforms (like >>>> Intel ICH SPI controller working under descriptor mode). >>>> >>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>> --- >>>> >>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>> index 0034a28..7d8c660 100644 >>>> --- a/drivers/mtd/spi/spi_flash.c >>>> +++ b/drivers/mtd/spi/spi_flash.c >>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>> if (IS_ERR_OR_NULL(info)) >>>> return -ENOENT; >>>> >>>> - /* Flash powers up read-only, so clear BP# bits */ >>>> + /* >>>> + * Flash powers up read-only, so clear BP# bits. >>>> + * >>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>> + * same status register as BP# bits, and we need preserve its original >>>> + * value during a reboot cycle as this is required by some platforms >>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>> + */ >>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>> write_sr(flash, 0); >>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>> + u8 sr = 0; >>>> + >>>> + read_sr(flash, &sr); >>>> + sr &= STATUS_QEB_MXIC; >>>> + write_sr(flash, sr); >>>> + } >>> >>> It doesn't make sense to have one(specific) controller fix to be >>> generic to all macronix chips, think about alternative. >>> >> >> This is no way to fix at the controller level. Actually this is >> nothing related to controller level. It's just the bootstrap settings >> (QE bit in this case) that cannot be overwritten by someone else >> (although it's seen on Intel, it might happen on some other >> architecture). The logic in the codes are having issues. Its comment >> says: clear BP# bits, but it clears QE bit for Macronix flash as well, >> which is wrong. The update was just to make sure the codes do as what >> its comment says. > > I believe QEB is same position for all Macronix chips, checked few > parts true? what if the supported chips from id tables doesn't have > QEB at-all means specific chip support upto dual? > Correct, QEB is in the same position (bit6) for all Macronix chips. If a chipset that does not support QEB, that bit (bit6) is reserved, and current patch still works. So current patch can correctly handle both situations. The issue here is that what we do here for the status register does NOT conform the comment. We only wanted to clear the #BP bits. We should NOT clear the QEB bit at all. Regards, Bin
Hi Bin, On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Jagan, > > On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >> Hi Bin, >> >> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi Jagan, >>> >>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>> status register as BP# bits, and we need preserve its original value >>>>> during a reboot cycle as this is required by some platforms (like >>>>> Intel ICH SPI controller working under descriptor mode). >>>>> >>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>> --- >>>>> >>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>> index 0034a28..7d8c660 100644 >>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>> if (IS_ERR_OR_NULL(info)) >>>>> return -ENOENT; >>>>> >>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>> + /* >>>>> + * Flash powers up read-only, so clear BP# bits. >>>>> + * >>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>> + * same status register as BP# bits, and we need preserve its original >>>>> + * value during a reboot cycle as this is required by some platforms >>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>> + */ >>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>> write_sr(flash, 0); >>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>> + u8 sr = 0; >>>>> + >>>>> + read_sr(flash, &sr); >>>>> + sr &= STATUS_QEB_MXIC; >>>>> + write_sr(flash, sr); Better assign sr with QEB for macronix and call write_sr once. >>>>> + } >>>> >>>> It doesn't make sense to have one(specific) controller fix to be >>>> generic to all macronix chips, think about alternative. >>>> >>> >>> This is no way to fix at the controller level. Actually this is >>> nothing related to controller level. It's just the bootstrap settings >>> (QE bit in this case) that cannot be overwritten by someone else >>> (although it's seen on Intel, it might happen on some other >>> architecture). The logic in the codes are having issues. Its comment >>> says: clear BP# bits, but it clears QE bit for Macronix flash as well, >>> which is wrong. The update was just to make sure the codes do as what >>> its comment says. >> >> I believe QEB is same position for all Macronix chips, checked few >> parts true? what if the supported chips from id tables doesn't have >> QEB at-all means specific chip support upto dual? >> > > Correct, QEB is in the same position (bit6) for all Macronix chips. If > a chipset that does not support QEB, that bit (bit6) is reserved, and > current patch still works. > > So current patch can correctly handle both situations. The issue here > is that what we do here for the status register does NOT conform the > comment. We only wanted to clear the #BP bits. We should NOT clear the > QEB bit at all. OK, thanks.
Hi Jagan, On Mon, Aug 14, 2017 at 12:58 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > Hi Bin, > > On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi Jagan, >> >> On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>> Hi Bin, >>> >>> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>> Hi Jagan, >>>> >>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>>> status register as BP# bits, and we need preserve its original value >>>>>> during a reboot cycle as this is required by some platforms (like >>>>>> Intel ICH SPI controller working under descriptor mode). >>>>>> >>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>>> --- >>>>>> >>>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>>> >>>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>>> index 0034a28..7d8c660 100644 >>>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>>> if (IS_ERR_OR_NULL(info)) >>>>>> return -ENOENT; >>>>>> >>>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>>> + /* >>>>>> + * Flash powers up read-only, so clear BP# bits. >>>>>> + * >>>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>>> + * same status register as BP# bits, and we need preserve its original >>>>>> + * value during a reboot cycle as this is required by some platforms >>>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>>> + */ >>>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>>> write_sr(flash, 0); >>>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>>> + u8 sr = 0; >>>>>> + >>>>>> + read_sr(flash, &sr); >>>>>> + sr &= STATUS_QEB_MXIC; >>>>>> + write_sr(flash, sr); > > Better assign sr with QEB for macronix and call write_sr once. For these Macronix flashes that does not support quard RW, QEB bit is reserved. Writing 1 to a reserved bit is not a good practice. > >>>>>> + } >>>>> >>>>> It doesn't make sense to have one(specific) controller fix to be >>>>> generic to all macronix chips, think about alternative. >>>>> >>>> >>>> This is no way to fix at the controller level. Actually this is >>>> nothing related to controller level. It's just the bootstrap settings >>>> (QE bit in this case) that cannot be overwritten by someone else >>>> (although it's seen on Intel, it might happen on some other >>>> architecture). The logic in the codes are having issues. Its comment >>>> says: clear BP# bits, but it clears QE bit for Macronix flash as well, >>>> which is wrong. The update was just to make sure the codes do as what >>>> its comment says. >>> >>> I believe QEB is same position for all Macronix chips, checked few >>> parts true? what if the supported chips from id tables doesn't have >>> QEB at-all means specific chip support upto dual? >>> >> >> Correct, QEB is in the same position (bit6) for all Macronix chips. If >> a chipset that does not support QEB, that bit (bit6) is reserved, and >> current patch still works. >> >> So current patch can correctly handle both situations. The issue here >> is that what we do here for the status register does NOT conform the >> comment. We only wanted to clear the #BP bits. We should NOT clear the >> QEB bit at all. > > OK, thanks. Regards, Bin
On Mon, Aug 14, 2017 at 10:34 AM, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Jagan, > > On Mon, Aug 14, 2017 at 12:58 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >> Hi Bin, >> >> On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi Jagan, >>> >>> On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>> Hi Bin, >>>> >>>> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>> Hi Jagan, >>>>> >>>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>>>> status register as BP# bits, and we need preserve its original value >>>>>>> during a reboot cycle as this is required by some platforms (like >>>>>>> Intel ICH SPI controller working under descriptor mode). >>>>>>> >>>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>>>> --- >>>>>>> >>>>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>>>> index 0034a28..7d8c660 100644 >>>>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>>>> if (IS_ERR_OR_NULL(info)) >>>>>>> return -ENOENT; >>>>>>> >>>>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>>>> + /* >>>>>>> + * Flash powers up read-only, so clear BP# bits. >>>>>>> + * >>>>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>>>> + * same status register as BP# bits, and we need preserve its original >>>>>>> + * value during a reboot cycle as this is required by some platforms >>>>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>>>> + */ >>>>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>>>> write_sr(flash, 0); >>>>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>>>> + u8 sr = 0; >>>>>>> + >>>>>>> + read_sr(flash, &sr); >>>>>>> + sr &= STATUS_QEB_MXIC; >>>>>>> + write_sr(flash, sr); >> >> Better assign sr with QEB for macronix and call write_sr once. > > For these Macronix flashes that does not support quard RW, QEB bit is > reserved. Writing 1 to a reserved bit is not a good practice. Yeah, i.e what I'm concern here. (apart from fixing comment) this issue came-up with your controller along with specific connected chip which support RW WEB. What if we couldn't preserve QEB? because if user need quad operation anyway code will check QEB if not it will enable. thanks!
Hi Jagan, On Mon, Aug 14, 2017 at 1:17 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > On Mon, Aug 14, 2017 at 10:34 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi Jagan, >> >> On Mon, Aug 14, 2017 at 12:58 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>> Hi Bin, >>> >>> On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>> Hi Jagan, >>>> >>>> On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>> Hi Bin, >>>>> >>>>> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>> Hi Jagan, >>>>>> >>>>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>>>>> status register as BP# bits, and we need preserve its original value >>>>>>>> during a reboot cycle as this is required by some platforms (like >>>>>>>> Intel ICH SPI controller working under descriptor mode). >>>>>>>> >>>>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>>>>> --- >>>>>>>> >>>>>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>>>>> >>>>>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>>>>> index 0034a28..7d8c660 100644 >>>>>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>>>>> if (IS_ERR_OR_NULL(info)) >>>>>>>> return -ENOENT; >>>>>>>> >>>>>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>>>>> + /* >>>>>>>> + * Flash powers up read-only, so clear BP# bits. >>>>>>>> + * >>>>>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>>>>> + * same status register as BP# bits, and we need preserve its original >>>>>>>> + * value during a reboot cycle as this is required by some platforms >>>>>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>>>>> + */ >>>>>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>>>>> write_sr(flash, 0); >>>>>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>>>>> + u8 sr = 0; >>>>>>>> + >>>>>>>> + read_sr(flash, &sr); >>>>>>>> + sr &= STATUS_QEB_MXIC; >>>>>>>> + write_sr(flash, sr); >>> >>> Better assign sr with QEB for macronix and call write_sr once. >> >> For these Macronix flashes that does not support quard RW, QEB bit is >> reserved. Writing 1 to a reserved bit is not a good practice. > > Yeah, i.e what I'm concern here. (apart from fixing comment) this > issue came-up with your controller along with specific connected chip > which support RW WEB. As I said, this is nothing related to the SPI controller driver. It can (technically) happen on other platforms. I don't understand what your concerns here. Your suggestion of writing SR once does not work. > > What if we couldn't preserve QEB? because if user need quad operation > anyway code will check QEB if not it will enable. The board simply bricks after a successful boot once. Because the QE bit is cleared by U-Boot during this successful boot, next time when the board powers-up, the SoC won't get a valid bootstrap setting from SPI flash. The bootstrap settings are stored in the SPI flash and there is a QE bit enable in the bootstrap setting. When SoC finds out the QE bit is turned on in the bootstrap setting but SPI flash's QE bit is off, the SoC refuses to boot. Regards, Bin
Hi Jagan, On Mon, Aug 14, 2017 at 1:35 PM, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Jagan, > > On Mon, Aug 14, 2017 at 1:17 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >> On Mon, Aug 14, 2017 at 10:34 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi Jagan, >>> >>> On Mon, Aug 14, 2017 at 12:58 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>> Hi Bin, >>>> >>>> On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>> Hi Jagan, >>>>> >>>>> On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>> Hi Bin, >>>>>> >>>>>> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>> Hi Jagan, >>>>>>> >>>>>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>>>>>> status register as BP# bits, and we need preserve its original value >>>>>>>>> during a reboot cycle as this is required by some platforms (like >>>>>>>>> Intel ICH SPI controller working under descriptor mode). >>>>>>>>> >>>>>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>>>>>> --- >>>>>>>>> >>>>>>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>>>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>>>>>> >>>>>>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>>>>>> index 0034a28..7d8c660 100644 >>>>>>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>>>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>>>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>>>>>> if (IS_ERR_OR_NULL(info)) >>>>>>>>> return -ENOENT; >>>>>>>>> >>>>>>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>>>>>> + /* >>>>>>>>> + * Flash powers up read-only, so clear BP# bits. >>>>>>>>> + * >>>>>>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>>>>>> + * same status register as BP# bits, and we need preserve its original >>>>>>>>> + * value during a reboot cycle as this is required by some platforms >>>>>>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>>>>>> + */ >>>>>>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>>>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>>>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>>>>>> write_sr(flash, 0); >>>>>>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>>>>>> + u8 sr = 0; >>>>>>>>> + >>>>>>>>> + read_sr(flash, &sr); >>>>>>>>> + sr &= STATUS_QEB_MXIC; >>>>>>>>> + write_sr(flash, sr); >>>> >>>> Better assign sr with QEB for macronix and call write_sr once. >>> >>> For these Macronix flashes that does not support quard RW, QEB bit is >>> reserved. Writing 1 to a reserved bit is not a good practice. >> >> Yeah, i.e what I'm concern here. (apart from fixing comment) this >> issue came-up with your controller along with specific connected chip >> which support RW WEB. > > As I said, this is nothing related to the SPI controller driver. It > can (technically) happen on other platforms. I don't understand what > your concerns here. Your suggestion of writing SR once does not work. > >> >> What if we couldn't preserve QEB? because if user need quad operation >> anyway code will check QEB if not it will enable. > > The board simply bricks after a successful boot once. Because the QE > bit is cleared by U-Boot during this successful boot, next time when > the board powers-up, the SoC won't get a valid bootstrap setting from > SPI flash. The bootstrap settings are stored in the SPI flash and > there is a QE bit enable in the bootstrap setting. When SoC finds out > the QE bit is turned on in the bootstrap setting but SPI flash's QE > bit is off, the SoC refuses to boot. > Sadly, this discussion ends to nowhere again. Can you please indicate your clear opinion on how to proceed? Regards, Bin
Hi Bin, On Wed, Aug 16, 2017 at 7:29 AM, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Jagan, > > On Mon, Aug 14, 2017 at 1:35 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi Jagan, >> >> On Mon, Aug 14, 2017 at 1:17 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>> On Mon, Aug 14, 2017 at 10:34 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>> Hi Jagan, >>>> >>>> On Mon, Aug 14, 2017 at 12:58 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>> Hi Bin, >>>>> >>>>> On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>> Hi Jagan, >>>>>> >>>>>> On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>> Hi Bin, >>>>>>> >>>>>>> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>> Hi Jagan, >>>>>>>> >>>>>>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>>>>>>> status register as BP# bits, and we need preserve its original value >>>>>>>>>> during a reboot cycle as this is required by some platforms (like >>>>>>>>>> Intel ICH SPI controller working under descriptor mode). >>>>>>>>>> >>>>>>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>>>>>>> --- >>>>>>>>>> >>>>>>>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>>>>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>>>>>>> >>>>>>>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>>>>>>> index 0034a28..7d8c660 100644 >>>>>>>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>>>>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>>>>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>>>>>>> if (IS_ERR_OR_NULL(info)) >>>>>>>>>> return -ENOENT; >>>>>>>>>> >>>>>>>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>>>>>>> + /* >>>>>>>>>> + * Flash powers up read-only, so clear BP# bits. >>>>>>>>>> + * >>>>>>>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>>>>>>> + * same status register as BP# bits, and we need preserve its original >>>>>>>>>> + * value during a reboot cycle as this is required by some platforms >>>>>>>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>>>>>>> + */ >>>>>>>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>>>>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>>>>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>>>>>>> write_sr(flash, 0); >>>>>>>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>>>>>>> + u8 sr = 0; >>>>>>>>>> + >>>>>>>>>> + read_sr(flash, &sr); >>>>>>>>>> + sr &= STATUS_QEB_MXIC; >>>>>>>>>> + write_sr(flash, sr); >>>>> >>>>> Better assign sr with QEB for macronix and call write_sr once. >>>> >>>> For these Macronix flashes that does not support quard RW, QEB bit is >>>> reserved. Writing 1 to a reserved bit is not a good practice. >>> >>> Yeah, i.e what I'm concern here. (apart from fixing comment) this >>> issue came-up with your controller along with specific connected chip >>> which support RW WEB. >> >> As I said, this is nothing related to the SPI controller driver. It >> can (technically) happen on other platforms. I don't understand what >> your concerns here. Your suggestion of writing SR once does not work. OK, then lets proceed with this. finally, I've made a change for easy readability [1], If you're OK I will apply this otherwise suggest any? [1] https://paste.ubuntu.com/25324972/ thanks!
Hi Jagan, On Wed, Aug 16, 2017 at 6:34 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: > Hi Bin, > > On Wed, Aug 16, 2017 at 7:29 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi Jagan, >> >> On Mon, Aug 14, 2017 at 1:35 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi Jagan, >>> >>> On Mon, Aug 14, 2017 at 1:17 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>> On Mon, Aug 14, 2017 at 10:34 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>> Hi Jagan, >>>>> >>>>> On Mon, Aug 14, 2017 at 12:58 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>> Hi Bin, >>>>>> >>>>>> On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>> Hi Jagan, >>>>>>> >>>>>>> On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>>> Hi Bin, >>>>>>>> >>>>>>>> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>>> Hi Jagan, >>>>>>>>> >>>>>>>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>>>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>>>>>>>> status register as BP# bits, and we need preserve its original value >>>>>>>>>>> during a reboot cycle as this is required by some platforms (like >>>>>>>>>>> Intel ICH SPI controller working under descriptor mode). >>>>>>>>>>> >>>>>>>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>>>>>>>> --- >>>>>>>>>>> >>>>>>>>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>>>>>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>>>>>>>> >>>>>>>>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>>>>>>>> index 0034a28..7d8c660 100644 >>>>>>>>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>>>>>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>>>>>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>>>>>>>> if (IS_ERR_OR_NULL(info)) >>>>>>>>>>> return -ENOENT; >>>>>>>>>>> >>>>>>>>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>>>>>>>> + /* >>>>>>>>>>> + * Flash powers up read-only, so clear BP# bits. >>>>>>>>>>> + * >>>>>>>>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>>>>>>>> + * same status register as BP# bits, and we need preserve its original >>>>>>>>>>> + * value during a reboot cycle as this is required by some platforms >>>>>>>>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>>>>>>>> + */ >>>>>>>>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>>>>>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>>>>>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>>>>>>>> write_sr(flash, 0); >>>>>>>>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>>>>>>>> + u8 sr = 0; >>>>>>>>>>> + >>>>>>>>>>> + read_sr(flash, &sr); >>>>>>>>>>> + sr &= STATUS_QEB_MXIC; >>>>>>>>>>> + write_sr(flash, sr); >>>>>> >>>>>> Better assign sr with QEB for macronix and call write_sr once. >>>>> >>>>> For these Macronix flashes that does not support quard RW, QEB bit is >>>>> reserved. Writing 1 to a reserved bit is not a good practice. >>>> >>>> Yeah, i.e what I'm concern here. (apart from fixing comment) this >>>> issue came-up with your controller along with specific connected chip >>>> which support RW WEB. >>> >>> As I said, this is nothing related to the SPI controller driver. It >>> can (technically) happen on other platforms. I don't understand what >>> your concerns here. Your suggestion of writing SR once does not work. > > OK, then lets proceed with this. > > finally, I've made a change for easy readability [1], If you're OK I > will apply this otherwise suggest any? > > [1] https://paste.ubuntu.com/25324972/ > Looks good. Please apply. Thanks! Regards, Bin
On Wed, Aug 16, 2017 at 5:56 PM, Bin Meng <bmeng.cn@gmail.com> wrote: > Hi Jagan, > > On Wed, Aug 16, 2017 at 6:34 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >> Hi Bin, >> >> On Wed, Aug 16, 2017 at 7:29 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi Jagan, >>> >>> On Mon, Aug 14, 2017 at 1:35 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>> Hi Jagan, >>>> >>>> On Mon, Aug 14, 2017 at 1:17 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>> On Mon, Aug 14, 2017 at 10:34 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>> Hi Jagan, >>>>>> >>>>>> On Mon, Aug 14, 2017 at 12:58 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>> Hi Bin, >>>>>>> >>>>>>> On Mon, Aug 14, 2017 at 8:07 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>> Hi Jagan, >>>>>>>> >>>>>>>> On Mon, Aug 14, 2017 at 1:22 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>>>> Hi Bin, >>>>>>>>> >>>>>>>>> On Wed, Aug 2, 2017 at 3:56 AM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>>>> Hi Jagan, >>>>>>>>>> >>>>>>>>>> On Wed, Aug 2, 2017 at 12:01 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote: >>>>>>>>>>> On Sun, Jul 23, 2017 at 8:14 PM, Bin Meng <bmeng.cn@gmail.com> wrote: >>>>>>>>>>>> On some flash (like Macronix), QE (quad enable) bit is in the same >>>>>>>>>>>> status register as BP# bits, and we need preserve its original value >>>>>>>>>>>> during a reboot cycle as this is required by some platforms (like >>>>>>>>>>>> Intel ICH SPI controller working under descriptor mode). >>>>>>>>>>>> >>>>>>>>>>>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >>>>>>>>>>>> --- >>>>>>>>>>>> >>>>>>>>>>>> drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- >>>>>>>>>>>> 1 file changed, 15 insertions(+), 2 deletions(-) >>>>>>>>>>>> >>>>>>>>>>>> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c >>>>>>>>>>>> index 0034a28..7d8c660 100644 >>>>>>>>>>>> --- a/drivers/mtd/spi/spi_flash.c >>>>>>>>>>>> +++ b/drivers/mtd/spi/spi_flash.c >>>>>>>>>>>> @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) >>>>>>>>>>>> if (IS_ERR_OR_NULL(info)) >>>>>>>>>>>> return -ENOENT; >>>>>>>>>>>> >>>>>>>>>>>> - /* Flash powers up read-only, so clear BP# bits */ >>>>>>>>>>>> + /* >>>>>>>>>>>> + * Flash powers up read-only, so clear BP# bits. >>>>>>>>>>>> + * >>>>>>>>>>>> + * Note on some flash (like Macronix), QE (quad enable) bit is in the >>>>>>>>>>>> + * same status register as BP# bits, and we need preserve its original >>>>>>>>>>>> + * value during a reboot cycle as this is required by some platforms >>>>>>>>>>>> + * (like Intel ICH SPI controller working under descriptor mode). >>>>>>>>>>>> + */ >>>>>>>>>>>> if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || >>>>>>>>>>>> - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || >>>>>>>>>>>> JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) >>>>>>>>>>>> write_sr(flash, 0); >>>>>>>>>>>> + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { >>>>>>>>>>>> + u8 sr = 0; >>>>>>>>>>>> + >>>>>>>>>>>> + read_sr(flash, &sr); >>>>>>>>>>>> + sr &= STATUS_QEB_MXIC; >>>>>>>>>>>> + write_sr(flash, sr); >>>>>>> >>>>>>> Better assign sr with QEB for macronix and call write_sr once. >>>>>> >>>>>> For these Macronix flashes that does not support quard RW, QEB bit is >>>>>> reserved. Writing 1 to a reserved bit is not a good practice. >>>>> >>>>> Yeah, i.e what I'm concern here. (apart from fixing comment) this >>>>> issue came-up with your controller along with specific connected chip >>>>> which support RW WEB. >>>> >>>> As I said, this is nothing related to the SPI controller driver. It >>>> can (technically) happen on other platforms. I don't understand what >>>> your concerns here. Your suggestion of writing SR once does not work. >> >> OK, then lets proceed with this. >> >> finally, I've made a change for easy readability [1], If you're OK I >> will apply this otherwise suggest any? >> >> [1] https://paste.ubuntu.com/25324972/ Applied to u-boot-spi/master thanks!
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 0034a28..7d8c660 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -947,11 +947,24 @@ int spi_flash_scan(struct spi_flash *flash) if (IS_ERR_OR_NULL(info)) return -ENOENT; - /* Flash powers up read-only, so clear BP# bits */ + /* + * Flash powers up read-only, so clear BP# bits. + * + * Note on some flash (like Macronix), QE (quad enable) bit is in the + * same status register as BP# bits, and we need preserve its original + * value during a reboot cycle as this is required by some platforms + * (like Intel ICH SPI controller working under descriptor mode). + */ if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || - JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX || JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) write_sr(flash, 0); + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { + u8 sr = 0; + + read_sr(flash, &sr); + sr &= STATUS_QEB_MXIC; + write_sr(flash, sr); + } flash->name = info->name; flash->memory_map = spi->memory_map;
On some flash (like Macronix), QE (quad enable) bit is in the same status register as BP# bits, and we need preserve its original value during a reboot cycle as this is required by some platforms (like Intel ICH SPI controller working under descriptor mode). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- drivers/mtd/spi/spi_flash.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)