From patchwork Fri Jul 21 17:06:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vicente Olivert Riera X-Patchwork-Id: 792226 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=busybox.net (client-ip=140.211.166.138; helo=whitealder.osuosl.org; envelope-from=buildroot-bounces@busybox.net; receiver=) Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xDccx61RQz9sNw for ; Sat, 22 Jul 2017 03:06:57 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 2A944886C4; Fri, 21 Jul 2017 17:06:55 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8slF+MeG-0uU; Fri, 21 Jul 2017 17:06:54 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by whitealder.osuosl.org (Postfix) with ESMTP id E9D5988700; Fri, 21 Jul 2017 17:06:53 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 1D1FB1C0146 for ; Fri, 21 Jul 2017 17:06:46 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 60FF5886DF for ; Fri, 21 Jul 2017 17:06:45 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pC5hhy86ohGL for ; Fri, 21 Jul 2017 17:06:44 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mailapp01.imgtec.com (mailapp01.imgtec.com [195.59.15.196]) by whitealder.osuosl.org (Postfix) with ESMTP id ACF52886D8 for ; Fri, 21 Jul 2017 17:06:44 +0000 (UTC) Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 0891A6FBBD58B for ; Fri, 21 Jul 2017 18:06:39 +0100 (IST) Received: from vriera-linux.le.imgtec.org (192.168.154.36) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 21 Jul 2017 18:06:43 +0100 From: Vicente Olivert Riera To: Date: Fri, 21 Jul 2017 18:06:35 +0100 Message-ID: <20170721170635.41202-5-Vincent.Riera@imgtec.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170721170635.41202-1-Vincent.Riera@imgtec.com> References: <20170721170635.41202-1-Vincent.Riera@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.154.36] Subject: [Buildroot] [PATCH 5/5] arch/mips: add MSA support X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" This patch adds support for MIPS SIMD Architecture (MSA) extension. This feature is available since MIPS release version 5 and is mutually exclusive with the MIPS DSP extension. Signed-off-by: Vicente Olivert Riera --- arch/Config.in | 3 +++ arch/Config.in.mips | 26 ++++++++++++++++++++++ toolchain/toolchain-common.in | 4 ++++ .../toolchain-external/pkg-toolchain-external.mk | 7 ++++++ toolchain/toolchain-wrapper.c | 3 +++ 5 files changed, 43 insertions(+) diff --git a/arch/Config.in b/arch/Config.in index 1183e8fdaf..e69d9f5d6f 100644 --- a/arch/Config.in +++ b/arch/Config.in @@ -273,6 +273,9 @@ config BR2_GCC_TARGET_FP32_MODE config BR2_GCC_TARGET_DSP string +config BR2_GCC_TARGET_MSA + string + config BR2_GCC_TARGET_CPU string diff --git a/arch/Config.in.mips b/arch/Config.in.mips index 099b607a23..ed1ac8e813 100644 --- a/arch/Config.in.mips +++ b/arch/Config.in.mips @@ -29,6 +29,8 @@ config BR2_MIPS_CPU_HAS_DSP_R2 bool config BR2_MIPS_CPU_HAS_DSP_R3 bool +config BR2_MIPS_CPU_HAS_MSA + bool # some cpu features are optional depending on the core config BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 @@ -37,6 +39,8 @@ config BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 bool config BR2_MIPS_CPU_MAYBE_HAS_DSP_R3 bool +config BR2_MIPS_CPU_MAYBE_HAS_MSA + bool choice prompt "Target Architecture Variant" @@ -65,6 +69,7 @@ config BR2_mips_32r5 select BR2_MIPS_CPU_MIPS32R5 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_32r6 bool "Generic MIPS32R6" depends on !BR2_ARCH_IS_64 @@ -72,6 +77,7 @@ config BR2_mips_32r6 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_interaptiv bool "interAptiv" depends on !BR2_ARCH_IS_64 @@ -93,6 +99,7 @@ config BR2_mips_p5600 depends on !BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS32R5 select BR2_MIPS_NAN_2008 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_xburst bool "XBurst" depends on !BR2_ARCH_IS_64 @@ -122,6 +129,7 @@ config BR2_mips_64r5 select BR2_MIPS_CPU_MIPS64R5 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_64r6 bool "Generic MIPS64R6" depends on BR2_ARCH_IS_64 @@ -129,14 +137,17 @@ config BR2_mips_64r6 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_i6400 bool "I6400" depends on BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS64R6 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_p6600 bool "P6600" depends on BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS64R6 + select BR2_MIPS_CPU_MAYBE_HAS_MSA endchoice @@ -263,6 +274,21 @@ config BR2_GCC_TARGET_DSP default "dspr2" if BR2_MIPS_CPU_HAS_DSP_R2 default "dspr3" if BR2_MIPS_CPU_HAS_DSP_R3 +config BR2_MIPS_ENABLE_MSA + bool "Enable MSA extension support" + depends on BR2_TOOLCHAIN_HAS_MMSA_OPTION + depends on BR2_MIPS_CPU_MAYBE_HAS_MSA && BR2_MIPS_FP32_MODE_64 + depends on !(BR2_MIPS_CPU_HAS_DSP_R1 || BR2_MIPS_CPU_HAS_DSP_R2 || BR2_MIPS_CPU_HAS_DSP_R3) + select BR2_MIPS_CPU_HAS_MSA + help + For some CPU cores, the MSA extension is optional. + Select this option if you are certain your particular + implementation has MSA support and you want to use it. + +config BR2_GCC_TARGET_MSA + default "no-msa" if !BR2_MIPS_CPU_HAS_MSA + default "msa" if BR2_MIPS_CPU_HAS_MSA + config BR2_ARCH default "mips" if BR2_mips default "mipsel" if BR2_mipsel diff --git a/toolchain/toolchain-common.in b/toolchain/toolchain-common.in index dcd8623650..4c53c72336 100644 --- a/toolchain/toolchain-common.in +++ b/toolchain/toolchain-common.in @@ -353,6 +353,10 @@ config BR2_TOOLCHAIN_HAS_MFPXX_OPTION config BR2_TOOLCHAIN_HAS_MDSPR3_OPTION bool +config BR2_TOOLCHAIN_HAS_MMSA_OPTION + bool + default y if BR2_TOOLCHAIN_GCC_AT_LEAST_7 + config BR2_TOOLCHAIN_HAS_SYNC_1 bool default y diff --git a/toolchain/toolchain-external/pkg-toolchain-external.mk b/toolchain/toolchain-external/pkg-toolchain-external.mk index 780372fc44..b428fea390 100644 --- a/toolchain/toolchain-external/pkg-toolchain-external.mk +++ b/toolchain/toolchain-external/pkg-toolchain-external.mk @@ -156,6 +156,7 @@ CC_TARGET_ARCH_ := $(call qstrip,$(BR2_GCC_TARGET_ARCH)) CC_TARGET_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_ABI)) CC_TARGET_NAN_ := $(call qstrip,$(BR2_GCC_TARGET_NAN)) CC_TARGET_DSP_ := $(call qstrip,$(BR2_GCC_TARGET_DSP)) +CC_TARGET_MSA_ := $(call qstrip,$(BR2_GCC_TARGET_MSA)) CC_TARGET_FP32_MODE_ := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE)) CC_TARGET_FPU_ := $(call qstrip,$(BR2_GCC_TARGET_FPU)) CC_TARGET_FLOAT_ABI_ := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI)) @@ -189,6 +190,12 @@ ifneq ($(CC_TARGET_DSP_),) TOOLCHAIN_EXTERNAL_CFLAGS += -m$(CC_TARGET_DSP_) TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_DSP='"$(CC_TARGET_DSP_)"' endif +ifeq ($(BR2_TOOLCHAIN_HAS_MMSA_OPTION),y) +ifneq ($(CC_TARGET_MSA_),) +TOOLCHAIN_EXTERNAL_CFLAGS += -m$(CC_TARGET_MSA_) +TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_MSA='"$(CC_TARGET_MSA_)"' +endif +endif ifneq ($(CC_TARGET_FP32_MODE_),) TOOLCHAIN_EXTERNAL_CFLAGS += -mfp$(CC_TARGET_FP32_MODE_) TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(CC_TARGET_FP32_MODE_)"' diff --git a/toolchain/toolchain-wrapper.c b/toolchain/toolchain-wrapper.c index 278cff05d8..9b9fd48f6f 100644 --- a/toolchain/toolchain-wrapper.c +++ b/toolchain/toolchain-wrapper.c @@ -57,6 +57,9 @@ static char *predef_args[] = { #ifdef BR_DSP "-m" BR_DSP, #endif +#ifdef BR_MSA + "-m" BR_MSA, +#endif #ifdef BR_FPU "-mfpu=" BR_FPU, #endif