| Message ID | 1500652067-23615-7-git-send-email-arbab@linux.vnet.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
Acked-by: Alistair Popple <alistair@popple.id.au> On Fri, 21 Jul 2017 10:47:43 AM Reza Arbab wrote: > POWER9 DD2 has added a second GPU memory BAR. Use it, but continue to > program things the old way on DD1 systems. > > Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> > Cc: Alistair Popple <alistair@popple.id.au> > Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> > Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> > --- > hw/npu2.c | 22 +++++++++++----------- > include/npu2-regs.h | 1 + > 2 files changed, 12 insertions(+), 11 deletions(-) > > diff --git a/hw/npu2.c b/hw/npu2.c > index a752ab5..5555159 100644 > --- a/hw/npu2.c > +++ b/hw/npu2.c > @@ -581,7 +581,7 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) > struct npu2 *p = ndev->npu; > int peers, mode; > uint32_t bdfn; > - uint64_t base, size, reg, val, old_val; > + uint64_t base, size, reg, val, old_val, gmb; > > /* Need to work out number of link peers. This amount to > * working out the maximum function number. So work start at > @@ -598,13 +598,16 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) > /* Base address is in GB */ > base >>= 30; > > + gmb = NPU2_GPU0_MEM_BAR; > + if (NPU2DEV_BRICK(ndev) && !is_p9dd1()) > + gmb = NPU2_GPU1_MEM_BAR; > + > reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), > - NPU2_BLOCK_SM_0, > - NPU2_GPU0_MEM_BAR); > + NPU2_BLOCK_SM_0, gmb); > > val = npu2_read(p, reg); > old_val = val; > - if (NPU2DEV_BRICK(ndev)) > + if (NPU2DEV_BRICK(ndev) && is_p9dd1()) > val <<= 32; > > val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, val, 4); > @@ -640,21 +643,18 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) > > mode += ndev->bdfn & 0x7; > val = SETFIELD(NPU2_MEM_BAR_MODE, val, mode); > - if (NPU2DEV_BRICK(ndev)) > + if (NPU2DEV_BRICK(ndev) && is_p9dd1()) > val = (old_val & 0xffffffff00000000) | (val >> 32); > > npu2_write(p, reg, val); > reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), > - NPU2_BLOCK_SM_1, > - NPU2_GPU0_MEM_BAR); > + NPU2_BLOCK_SM_1, gmb); > npu2_write(p, reg, val); > reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), > - NPU2_BLOCK_SM_2, > - NPU2_GPU0_MEM_BAR); > + NPU2_BLOCK_SM_2, gmb); > npu2_write(p, reg, val); > reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), > - NPU2_BLOCK_SM_3, > - NPU2_GPU0_MEM_BAR); > + NPU2_BLOCK_SM_3, gmb); > npu2_write(p, reg, val); > > return 0; > diff --git a/include/npu2-regs.h b/include/npu2-regs.h > index 4b86f6f..fb85729 100644 > --- a/include/npu2-regs.h > +++ b/include/npu2-regs.h > @@ -101,6 +101,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); > #define NPU2_PB_EPSILON 0x010 > #define NPU2_TIMER_CFG 0x018 > #define NPU2_GPU0_MEM_BAR 0x020 > +#define NPU2_GPU1_MEM_BAR 0x028 > #define NPU2_MEM_BAR_SEL_MEM PPC_BITMASK(0,2) > #define NPU2_MEM_BAR_GROUP PPC_BITMASK(3,6) > #define NPU2_MEM_BAR_CHIP PPC_BITMASK(7,9) >
diff --git a/hw/npu2.c b/hw/npu2.c index a752ab5..5555159 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -581,7 +581,7 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) struct npu2 *p = ndev->npu; int peers, mode; uint32_t bdfn; - uint64_t base, size, reg, val, old_val; + uint64_t base, size, reg, val, old_val, gmb; /* Need to work out number of link peers. This amount to * working out the maximum function number. So work start at @@ -598,13 +598,16 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) /* Base address is in GB */ base >>= 30; + gmb = NPU2_GPU0_MEM_BAR; + if (NPU2DEV_BRICK(ndev) && !is_p9dd1()) + gmb = NPU2_GPU1_MEM_BAR; + reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), - NPU2_BLOCK_SM_0, - NPU2_GPU0_MEM_BAR); + NPU2_BLOCK_SM_0, gmb); val = npu2_read(p, reg); old_val = val; - if (NPU2DEV_BRICK(ndev)) + if (NPU2DEV_BRICK(ndev) && is_p9dd1()) val <<= 32; val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, val, 4); @@ -640,21 +643,18 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) mode += ndev->bdfn & 0x7; val = SETFIELD(NPU2_MEM_BAR_MODE, val, mode); - if (NPU2DEV_BRICK(ndev)) + if (NPU2DEV_BRICK(ndev) && is_p9dd1()) val = (old_val & 0xffffffff00000000) | (val >> 32); npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), - NPU2_BLOCK_SM_1, - NPU2_GPU0_MEM_BAR); + NPU2_BLOCK_SM_1, gmb); npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), - NPU2_BLOCK_SM_2, - NPU2_GPU0_MEM_BAR); + NPU2_BLOCK_SM_2, gmb); npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), - NPU2_BLOCK_SM_3, - NPU2_GPU0_MEM_BAR); + NPU2_BLOCK_SM_3, gmb); npu2_write(p, reg, val); return 0; diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 4b86f6f..fb85729 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -101,6 +101,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_PB_EPSILON 0x010 #define NPU2_TIMER_CFG 0x018 #define NPU2_GPU0_MEM_BAR 0x020 +#define NPU2_GPU1_MEM_BAR 0x028 #define NPU2_MEM_BAR_SEL_MEM PPC_BITMASK(0,2) #define NPU2_MEM_BAR_GROUP PPC_BITMASK(3,6) #define NPU2_MEM_BAR_CHIP PPC_BITMASK(7,9)
POWER9 DD2 has added a second GPU memory BAR. Use it, but continue to program things the old way on DD1 systems. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Alistair Popple <alistair@popple.id.au> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> --- hw/npu2.c | 22 +++++++++++----------- include/npu2-regs.h | 1 + 2 files changed, 12 insertions(+), 11 deletions(-)