[1/3] sparc64: recognize and support sparc M8 cpu type

Hi Sam,

>> +++ b/arch/sparc/kernel/head_64.S
>> @@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
>>   	cmp	%g2, '7'
>>   	be,pt	%xcc, 5f
>>   	 mov	SUN4V_CHIP_SPARC_M7, %g4
>> +	cmp	%g2, '8'
>> +	be,pt	%xcc, 5f
>> +	 mov	SUN4V_CHIP_SPARC_M8, %g4
>
> Could we use this opportunity to create properly named
> constants for '7', '8', 'N' etc, rather than harcoding these
> in some assembler files.
> (Obviously in a separate patch).

Would this work?

- Allen
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Hi Allen,

On 21/07/2017 10:21, Allen wrote:
> 
> Hi Sam,
> 
>>> +++ b/arch/sparc/kernel/head_64.S
>>> @@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
>>>       cmp    %g2, '7'
>>>       be,pt    %xcc, 5f
>>>        mov    SUN4V_CHIP_SPARC_M7, %g4
>>> +    cmp    %g2, '8'
>>> +    be,pt    %xcc, 5f
>>> +     mov    SUN4V_CHIP_SPARC_M8, %g4
>>
>> Could we use this opportunity to create properly named
>> constants for '7', '8', 'N' etc, rather than harcoding these
>> in some assembler files.
>> (Obviously in a separate patch).
> 
> Would this work?
> 
> diff --git a/arch/sparc/include/asm/spitfire.h
> b/arch/sparc/include/asm/spitfire.h
> index ba3a655..c23b24e 100644
> --- a/arch/sparc/include/asm/spitfire.h
> +++ b/arch/sparc/include/asm/spitfire.h
> @@ -52,6 +52,17 @@
>  #define SUN4V_CHIP_SPARC_SN    0x8b
>  #define SUN4V_CHIP_UNKNOWN     0xff
> 
> +/* CPU Constants */
> +#define NIAGARA1               1
> +#define NIAGARA2               2
> +#define NIAGARA3               3
> +#define NIAGARA4               4
> +#define NIAGARA5               5
> +#define M6                     6
> +#define M7                     7
> +#define M8                     8
All of the above were character constants in the original.

Regards

Richard

> +#define SONOMA1                        ('N')
> +
>  #ifndef __ASSEMBLY__
> 
>  enum ultra_tlb_layout {
> diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
> index afcd4ca..46c12d6 100644
> --- a/arch/sparc/kernel/head_64.S
> +++ b/arch/sparc/kernel/head_64.S
> @@ -424,25 +424,25 @@ EXPORT_SYMBOL(sun4v_chip_type)
>          nop
> 
>  70:    ldub    [%g1 + 7], %g2
> -       cmp     %g2, '3'
> +       cmp     %g2, NIAGARA3
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_NIAGARA3, %g4
> -       cmp     %g2, '4'
> +       cmp     %g2, NIAGARA4
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_NIAGARA4, %g4
> -       cmp     %g2, '5'
> +       cmp     %g2, NIAGARA5
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_NIAGARA5, %g4
> -       cmp     %g2, '6'
> +       cmp     %g2, M6
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_SPARC_M6, %g4
> -       cmp     %g2, '7'
> +       cmp     %g2, M7
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_SPARC_M7, %g4
> -       cmp     %g2, '8'
> +       cmp     %g2, M8
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_SPARC_M8, %g4
> -       cmp     %g2, 'N'
> +       cmp     %g2, SONOMA1
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_SPARC_SN, %g4
>         ba,pt   %xcc, 49f
> @@ -451,10 +451,10 @@ EXPORT_SYMBOL(sun4v_chip_type)
>  91:    sethi   %hi(prom_cpu_compatible), %g1
>         or      %g1, %lo(prom_cpu_compatible), %g1
>         ldub    [%g1 + 17], %g2
> -       cmp     %g2, '1'
> +       cmp     %g2, NIAGARA1
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_NIAGARA1, %g4
> -       cmp     %g2, '2'
> +       cmp     %g2, NIAGARA2
>         be,pt   %xcc, 5f
>          mov    SUN4V_CHIP_NIAGARA2, %g4
> 
> - Allen
> -- 
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Hi Richard,

>> +/* CPU Constants */
>> +#define NIAGARA1               1
>> +#define NIAGARA2               2
>> +#define NIAGARA3               3
>> +#define NIAGARA4               4
>> +#define NIAGARA5               5
>> +#define M6                     6
>> +#define M7                     7
>> +#define M8                     8
> All of the above were character constants in the original.
>

  Yep. It was just a rough diff for RFC. If the thought is fine, I'll 
clean and send out a patch.

- Allen
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On Fri, Jul 21, 2017 at 02:51:59PM +0530, Allen wrote:
> 
> Hi Sam,
> 
> >>+++ b/arch/sparc/kernel/head_64.S
> >>@@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
> >>  	cmp	%g2, '7'
> >>  	be,pt	%xcc, 5f
> >>  	 mov	SUN4V_CHIP_SPARC_M7, %g4
> >>+	cmp	%g2, '8'
> >>+	be,pt	%xcc, 5f
> >>+	 mov	SUN4V_CHIP_SPARC_M8, %g4
> >
> >Could we use this opportunity to create properly named
> >constants for '7', '8', 'N' etc, rather than harcoding these
> >in some assembler files.
> >(Obviously in a separate patch).
> 
> Would this work?

It is way better than the hardcoded values.
If the vales have any sort of name in the sparc specs
the values shall be prefixed with this.
Otherwise something like
CPU_ID_xxx

And maybe add an intro comment like this:
/* following CPU_ID_xxx constants are used to identify the
 * CPU type in the setup phase (see xxx.S)
*/

(As character constants, but that part is obvious).

	Sam

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From: Allen <allen.pais@oracle.com>
Date: Fri, 21 Jul 2017 14:51:59 +0530

> 
> Hi Sam,
> 
>>> +++ b/arch/sparc/kernel/head_64.S
>>> @@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
>>>   	cmp	%g2, '7'
>>>   	be,pt	%xcc, 5f
>>>   	 mov	SUN4V_CHIP_SPARC_M7, %g4
>>> +	cmp	%g2, '8'
>>> +	be,pt	%xcc, 5f
>>> +	 mov	SUN4V_CHIP_SPARC_M8, %g4
>>
>> Could we use this opportunity to create properly named
>> constants for '7', '8', 'N' etc, rather than harcoding these
>> in some assembler files.
>> (Obviously in a separate patch).
> 
> Would this work?

That won't even boot.

You're changing an ASCII character '?' value into a raw
constant.
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