| Message ID | 90d39b29dbe471d5a6ca0f75c12de2600c477c30.1500541666.git.michal.simek@xilinx.com |
|---|---|
| State | Accepted |
| Commit | 926870478d1fd5e8cf6a38716c9cf1ae845435e1 |
| Delegated to: | Michal Simek |
| Headers | show |
diff --git a/include/zynqmppl.h b/include/zynqmppl.h index fb5200ec84a6..4c8c2f88f04c 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -20,7 +20,7 @@ #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 -#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT) +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT) extern struct xilinx_fpga_op zynqmp_op;
Mask should start from the first bit - using 0xe is just wrong. 3bits are used that's why 0x7 mask is correct. This patch is fixing silicon ID code detection. Previous behavior was that bit0 was completely ignored. Issue was found on 2eg chip detection. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- include/zynqmppl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)