From patchwork Thu Jul 20 00:29:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TWljaGHFgiBNaXJvc8WCYXc=?= X-Patchwork-Id: 791316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=rere.qmqm.pl header.i=@rere.qmqm.pl header.b="Y+CEXNGp"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xCZXW20Xnz9t36 for ; Thu, 20 Jul 2017 10:29:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754144AbdGTA33 (ORCPT ); Wed, 19 Jul 2017 20:29:29 -0400 Received: from rere.qmqm.pl ([91.227.64.183]:50912 "EHLO rere.qmqm.pl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754373AbdGTA31 (ORCPT ); Wed, 19 Jul 2017 20:29:27 -0400 Received: from remote.user (localhost [127.0.0.1]) by rere.qmqm.pl (Postfix) with ESMTPSA id 24C9B32F; Thu, 20 Jul 2017 02:29:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=rere.qmqm.pl; s=1; t=1500510566; bh=p22yTEUeumLFHwGFFffb3eCys9UeL9qwXKmEXeC1GSI=; h=Date:In-Reply-To:References:From:Subject:To:From; b=Y+CEXNGpqMrBtPcQceUWZdvrgx0hF2CuEuaWmwlE9JlnKj3zaNPh2+8UoA2We/Q4N 2wKd9QUrJBWt2P0im8R7qSBWlG3cSVBh8uawSdIY6swU/Tn3b0+tX8CUJDG5Paia90 oiBESjQgYO2jVEi/tRT69/fonNqAbJ2EHhPBYRPxaCHozqJJOkVhykZAJ6+/Jt7huy C5eb7kRZy4iZXyk05H0vQ0Ij1X4URv4QCJpFOi5aW1vzpL3i1APg2cw+TQP6i4KdFS i6XV1rK3RxrOn5EKUQir6qv86Dl8uoP+70bS94Iiqf9T1g7BVrOV9wVqwJuBmiH3li G3LY8KAC0hCjg== X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.99.2 at rere Date: Thu, 20 Jul 2017 02:29:25 +0200 Message-Id: <22bba1196e745a5bdf66bd449bee7ccc17bd4761.1500510157.git.mirq-linux@rere.qmqm.pl> In-Reply-To: References: From: =?UTF-8?q?Micha=C5=82=20Miros=C5=82aw?= Subject: [PATCH 8/9] ARM: tegra: avoid touching Secure registers in reset handler MIME-Version: 1.0 To: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This allows secondary CPUs to boot with Trusted Foundations firmware. Signed-off-by: Michał Mirosław --- arch/arm/mach-tegra/reset-handler.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index aae7f5961563..f642032a5a08 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -143,6 +143,8 @@ ENTRY(__tegra_cpu_reset_handler) cpsid aif, 0x13 @ SVC mode, interrupts disabled tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 + +#ifdef CONFIG_ARCH_ASSUME_SECURE_PLATFORM #ifdef CONFIG_ARCH_TEGRA_2x_SOC t20_check: cmp r6, #TEGRA20 @@ -172,6 +174,7 @@ t30_errata: b after_errata after_t30_check: #endif +#endif /* CONFIG_ARCH_ASSUME_SECURE_PLATFORM */ after_errata: mrc p15, 0, r10, c0, c0, 5 @ MPIDR and r10, r10, #0x3 @ R10 = CPU number