[v2,12/25] dt-bindings: qcom_nandc: QPIC NAND documentation
diff mbox

Message ID 1500464893-11352-13-git-send-email-absahu@codeaurora.org
State Superseded
Delegated to: Boris Brezillon
Headers show

Commit Message

Abhishek Sahu July 19, 2017, 11:48 a.m. UTC
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
   while EBI2 NAND uses only single ADM channel.
3. CRCI is only required for ADM DMA and its not required for
   QPIC NAND.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 .../devicetree/bindings/mtd/qcom_nandc.txt         | 54 ++++++++++++++++++++--
 1 file changed, 51 insertions(+), 3 deletions(-)

Comments

Boris Brezillon July 19, 2017, 7:39 p.m. UTC | #1
On Wed, 19 Jul 2017 17:18:00 +0530
Abhishek Sahu <absahu@codeaurora.org> wrote:

> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>    while EBI2 NAND uses only single ADM channel.
> 3. CRCI is only required for ADM DMA and its not required for
>    QPIC NAND.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 54 ++++++++++++++++++++--
>  1 file changed, 51 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index b24adfe..8efaeb0 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,13 +1,15 @@
>  * Qualcomm NAND controller
>  
>  Required properties:
> -- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
> -			DMA like IPQ8064.
> -
> +- compatible:		must be one of the following:
> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
>  - reg:			MMIO address range
>  - clocks:		must contain core clock and always on clock
>  - clock-names:		must contain "core" for the core clock and "aon" for the
>  			always on clock
> +
> +EBI2 specific properties:
>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
>  			controller node and the channel number to be used for
>  			NAND. Refer to dma.txt and qcom_adm.txt for more details
> @@ -18,6 +20,12 @@ Required properties:
>  - qcom,data-crci:	must contain the ADM data type CRCI block instance
>  			number specified for the NAND controller on the given
>  			platform
> +
> +QPIC specific properties:
> +- dmas:			DMA specifier, consisting of a phandle to the BAM DMA
> +			and the channel number to be used for NAND. Refer to
> +			dma.txt, qcom_bam_dma.txt for more details
> +- dma-names:		must contain all 3 channel names : "tx", "rx", "cmd"
>  - #address-cells:	<1> - subnodes give the chip-select number
>  - #size-cells:		<0>
>  
> @@ -84,3 +92,43 @@ nand@1ac00000 {
>  		};
>  	};
>  };
> +
> +nand@79b0000 {

I think I already mentioned I'd prefer to have

nand-controller@xxxx {

> +	compatible = "qcom,qpic-nandc-v1.4.0";
> +	reg = <0x79b0000 0x1000>;
> +
> +	clocks = <&gcc GCC_QPIC_CLK>,
> +		<&gcc GCC_QPIC_AHB_CLK>;
> +	clock-names = "core", "aon";
> +
> +	dmas = <&qpicbam 0>,
> +		<&qpicbam 1>,
> +		<&qpicbam 2>;
> +	dma-names = "tx", "rx", "cmd";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	nandcs@0 {

and
	nand@x {

here.

> +		reg = <0>;
> +		nand-ecc-strength = <4>;
> +		nand-ecc-step-size = <512>;
> +		nand-bus-width = <8>;
> +
> +		partitions {
> +			compatible = "fixed-partitions";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			partition@0 {
> +				label = "boot-nand";
> +				reg = <0 0x58a0000>;
> +			};
> +
> +			partition@58a0000 {
> +				label = "fs-nand";
> +				reg = <0x58a0000 0x4000000>;
> +			};
> +		};
> +	};
> +};
Abhishek Sahu July 20, 2017, 5:33 a.m. UTC | #2
On 2017-07-20 01:09, Boris Brezillon wrote:
> On Wed, 19 Jul 2017 17:18:00 +0530
> Abhishek Sahu <absahu@codeaurora.org> wrote:
> 
>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>>    while EBI2 NAND uses only single ADM channel.
>> 3. CRCI is only required for ADM DMA and its not required for
>>    QPIC NAND.
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 54 
>> ++++++++++++++++++++--
>>  1 file changed, 51 insertions(+), 3 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt 
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index b24adfe..8efaeb0 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -1,13 +1,15 @@
>>  * Qualcomm NAND controller
>> 
>>  Required properties:
>> -- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
>> -			DMA like IPQ8064.
>> -
>> +- compatible:		must be one of the following:
>> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA 
>> like IPQ4019.
>>  - reg:			MMIO address range
>>  - clocks:		must contain core clock and always on clock
>>  - clock-names:		must contain "core" for the core clock and "aon" for 
>> the
>>  			always on clock
>> +
>> +EBI2 specific properties:
>>  - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
>>  			controller node and the channel number to be used for
>>  			NAND. Refer to dma.txt and qcom_adm.txt for more details
>> @@ -18,6 +20,12 @@ Required properties:
>>  - qcom,data-crci:	must contain the ADM data type CRCI block instance
>>  			number specified for the NAND controller on the given
>>  			platform
>> +
>> +QPIC specific properties:
>> +- dmas:			DMA specifier, consisting of a phandle to the BAM DMA
>> +			and the channel number to be used for NAND. Refer to
>> +			dma.txt, qcom_bam_dma.txt for more details
>> +- dma-names:		must contain all 3 channel names : "tx", "rx", "cmd"
>>  - #address-cells:	<1> - subnodes give the chip-select number
>>  - #size-cells:		<0>
>> 
>> @@ -84,3 +92,43 @@ nand@1ac00000 {
>>  		};
>>  	};
>>  };
>> +
>> +nand@79b0000 {
> 
> I think I already mentioned I'd prefer to have
> 
> nand-controller@xxxx {
> 

  Sorry. I Missed that part. I will change it in v3.

>> +	compatible = "qcom,qpic-nandc-v1.4.0";
>> +	reg = <0x79b0000 0x1000>;
>> +
>> +	clocks = <&gcc GCC_QPIC_CLK>,
>> +		<&gcc GCC_QPIC_AHB_CLK>;
>> +	clock-names = "core", "aon";
>> +
>> +	dmas = <&qpicbam 0>,
>> +		<&qpicbam 1>,
>> +		<&qpicbam 2>;
>> +	dma-names = "tx", "rx", "cmd";
>> +
>> +	#address-cells = <1>;
>> +	#size-cells = <0>;
>> +
>> +	nandcs@0 {
> 
> and
> 	nand@x {
> 
> here.
> 

  Will change this also.

>> +		reg = <0>;
>> +		nand-ecc-strength = <4>;
>> +		nand-ecc-step-size = <512>;
>> +		nand-bus-width = <8>;
>> +
>> +		partitions {
>> +			compatible = "fixed-partitions";
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +
>> +			partition@0 {
>> +				label = "boot-nand";
>> +				reg = <0 0x58a0000>;
>> +			};
>> +
>> +			partition@58a0000 {
>> +				label = "fs-nand";
>> +				reg = <0x58a0000 0x4000000>;
>> +			};
>> +		};
>> +	};
>> +};
Rob Herring July 24, 2017, 7:17 p.m. UTC | #3
On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>    while EBI2 NAND uses only single ADM channel.
> 3. CRCI is only required for ADM DMA and its not required for
>    QPIC NAND.
> 
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> ---
>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 54 ++++++++++++++++++++--
>  1 file changed, 51 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> index b24adfe..8efaeb0 100644
> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> @@ -1,13 +1,15 @@
>  * Qualcomm NAND controller
>  
>  Required properties:
> -- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
> -			DMA like IPQ8064.
> -
> +- compatible:		must be one of the following:
> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.

Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific 
compatible strings.

Rob
Abhishek Sahu July 25, 2017, 6:43 p.m. UTC | #4
On 2017-07-25 00:47, Rob Herring wrote:
> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>>    while EBI2 NAND uses only single ADM channel.
>> 3. CRCI is only required for ADM DMA and its not required for
>>    QPIC NAND.
>> 
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> ---
>>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 54 
>> ++++++++++++++++++++--
>>  1 file changed, 51 insertions(+), 3 deletions(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt 
>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> index b24adfe..8efaeb0 100644
>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> @@ -1,13 +1,15 @@
>>  * Qualcomm NAND controller
>> 
>>  Required properties:
>> -- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
>> -			DMA like IPQ8064.
>> -
>> +- compatible:		must be one of the following:
>> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA 
>> like IPQ4019.
> 
> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
> compatible strings.

  We have 3 versions of NAND HW currently.
  EBI2,
  QPIC version 1.4.0
  QPIC version 1.5.0

  and multiple Qualcomm SoCs which use any one of these.

  The original plan was to have compatible string for NAND version since
  same NAND hardware is being in different SoC and SoC dtsi will simply
  use its NAND version compatible string like other Qualcomm hardwares

  
http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
  
http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt

> 
> Rob
Abhishek Sahu July 31, 2017, 4:05 p.m. UTC | #5
On 2017-07-26 00:13, Abhishek Sahu wrote:
> On 2017-07-25 00:47, Rob Herring wrote:
>> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
>>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>>>    while EBI2 NAND uses only single ADM channel.
>>> 3. CRCI is only required for ADM DMA and its not required for
>>>    QPIC NAND.
>>> 
>>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>>> ---
>>>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 54 
>>> ++++++++++++++++++++--
>>>  1 file changed, 51 insertions(+), 3 deletions(-)
>>> 
>>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt 
>>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>>> index b24adfe..8efaeb0 100644
>>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>>> @@ -1,13 +1,15 @@
>>>  * Qualcomm NAND controller
>>> 
>>>  Required properties:
>>> -- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses 
>>> ADM
>>> -			DMA like IPQ8064.
>>> -
>>> +- compatible:		must be one of the following:
>>> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>>> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA 
>>> like IPQ4019.
>> 
>> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
>> compatible strings.
> 
>  We have 3 versions of NAND HW currently.
>  EBI2,
>  QPIC version 1.4.0
>  QPIC version 1.5.0
> 
>  and multiple Qualcomm SoCs which use any one of these.
> 
>  The original plan was to have compatible string for NAND version since
>  same NAND hardware is being in different SoC and SoC dtsi will simply
>  use its NAND version compatible string like other Qualcomm hardwares
> 
> 
> http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> 
> http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
> 

  Following are the partial list for NAND controller and supported
  SoC

   EBI2:          IPQ8064, APQ8064, MSM7xx, MDM9x15
   QPIC v1.4.0    MDM9x25, MDM9x35, MDM9x45, IPQ4019
   QPIC v1.5.0    MDM9x55, IPQ8074

  so could we use NAND controller specific compatible strings instead of 
SoC
  since it will easy to maintain?

>> 
>> Rob
Boris Brezillon Aug. 4, 2017, 12:45 p.m. UTC | #6
On Mon, 31 Jul 2017 21:35:57 +0530
Abhishek Sahu <absahu@codeaurora.org> wrote:

> On 2017-07-26 00:13, Abhishek Sahu wrote:
> > On 2017-07-25 00:47, Rob Herring wrote:  
> >> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:  
> >>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> >>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
> >>>    while EBI2 NAND uses only single ADM channel.
> >>> 3. CRCI is only required for ADM DMA and its not required for
> >>>    QPIC NAND.
> >>> 
> >>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> >>> ---
> >>>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 54 
> >>> ++++++++++++++++++++--
> >>>  1 file changed, 51 insertions(+), 3 deletions(-)
> >>> 
> >>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt 
> >>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >>> index b24adfe..8efaeb0 100644
> >>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >>> @@ -1,13 +1,15 @@
> >>>  * Qualcomm NAND controller
> >>> 
> >>>  Required properties:
> >>> -- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses 
> >>> ADM
> >>> -			DMA like IPQ8064.
> >>> -
> >>> +- compatible:		must be one of the following:
> >>> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> >>> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA 
> >>> like IPQ4019.  
> >> 
> >> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
> >> compatible strings.  
> > 
> >  We have 3 versions of NAND HW currently.
> >  EBI2,
> >  QPIC version 1.4.0
> >  QPIC version 1.5.0
> > 
> >  and multiple Qualcomm SoCs which use any one of these.
> > 
> >  The original plan was to have compatible string for NAND version since
> >  same NAND hardware is being in different SoC and SoC dtsi will simply
> >  use its NAND version compatible string like other Qualcomm hardwares
> > 
> > 
> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> > 
> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
> >   
> 
>   Following are the partial list for NAND controller and supported
>   SoC
> 
>    EBI2:          IPQ8064, APQ8064, MSM7xx, MDM9x15
>    QPIC v1.4.0    MDM9x25, MDM9x35, MDM9x45, IPQ4019
>    QPIC v1.5.0    MDM9x55, IPQ8074
> 
>   so could we use NAND controller specific compatible strings instead of 
> SoC
>   since it will easy to maintain?

Nope, though you can re-use the compatible of an old SoC for new SoCs
if the IP did not change.

For example:

- EBI2: compatible = "qcom,ipq8064"
- QPIC 1.4: compatible = "qcom,mdm9x25"
- QPIC 1.5: compatible = "qcom,mdm9x55"

Note that we usually pick the oldest SoC that started embedding an IP
when choosing the compatible. So my suggestion assumes IPQ8064 is older
than APQ8064, MSM7xx and MDM9x15.
Abhishek Sahu Aug. 4, 2017, 1:11 p.m. UTC | #7
On 2017-08-04 18:15, Boris Brezillon wrote:
> On Mon, 31 Jul 2017 21:35:57 +0530
> Abhishek Sahu <absahu@codeaurora.org> wrote:
> 
>> On 2017-07-26 00:13, Abhishek Sahu wrote:
>> > On 2017-07-25 00:47, Rob Herring wrote:
>> >> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
>> >>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
>> >>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
>> >>>    while EBI2 NAND uses only single ADM channel.
>> >>> 3. CRCI is only required for ADM DMA and its not required for
>> >>>    QPIC NAND.
>> >>>
>> >>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>> >>> ---
>> >>>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 54
>> >>> ++++++++++++++++++++--
>> >>>  1 file changed, 51 insertions(+), 3 deletions(-)
>> >>>
>> >>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> >>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> >>> index b24adfe..8efaeb0 100644
>> >>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> >>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
>> >>> @@ -1,13 +1,15 @@
>> >>>  * Qualcomm NAND controller
>> >>>
>> >>>  Required properties:
>> >>> -- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses
>> >>> ADM
>> >>> -			DMA like IPQ8064.
>> >>> -
>> >>> +- compatible:		must be one of the following:
>> >>> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
>> >>> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
>> >>> like IPQ4019.
>> >>
>> >> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
>> >> compatible strings.
>> >
>> >  We have 3 versions of NAND HW currently.
>> >  EBI2,
>> >  QPIC version 1.4.0
>> >  QPIC version 1.5.0
>> >
>> >  and multiple Qualcomm SoCs which use any one of these.
>> >
>> >  The original plan was to have compatible string for NAND version since
>> >  same NAND hardware is being in different SoC and SoC dtsi will simply
>> >  use its NAND version compatible string like other Qualcomm hardwares
>> >
>> >
>> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
>> >
>> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
>> >
>> 
>>   Following are the partial list for NAND controller and supported
>>   SoC
>> 
>>    EBI2:          IPQ8064, APQ8064, MSM7xx, MDM9x15
>>    QPIC v1.4.0    MDM9x25, MDM9x35, MDM9x45, IPQ4019
>>    QPIC v1.5.0    MDM9x55, IPQ8074
>> 
>>   so could we use NAND controller specific compatible strings instead 
>> of
>> SoC
>>   since it will easy to maintain?
> 
> Nope, though you can re-use the compatible of an old SoC for new SoCs
> if the IP did not change.
> 
> For example:
> 
> - EBI2: compatible = "qcom,ipq8064"
> - QPIC 1.4: compatible = "qcom,mdm9x25"
> - QPIC 1.5: compatible = "qcom,mdm9x55"
> 
> Note that we usually pick the oldest SoC that started embedding an IP
> when choosing the compatible. So my suggestion assumes IPQ8064 is older
> than APQ8064, MSM7xx and MDM9x15.

  Thanks Boris for detailed clarification.
  Then I will change the patch to use SoC specific compatible string.

  Its better to use qcom,ipq4019 for 1.4.0 and qcom,ipq8074 for 1.5.0
  since we don't have other SoC in upstream and I have tested the
  NAND driver on these IPQ SoC's.
Boris Brezillon Aug. 4, 2017, 1:22 p.m. UTC | #8
On Fri, 04 Aug 2017 18:41:20 +0530
Abhishek Sahu <absahu@codeaurora.org> wrote:

> On 2017-08-04 18:15, Boris Brezillon wrote:
> > On Mon, 31 Jul 2017 21:35:57 +0530
> > Abhishek Sahu <absahu@codeaurora.org> wrote:
> >   
> >> On 2017-07-26 00:13, Abhishek Sahu wrote:  
> >> > On 2017-07-25 00:47, Rob Herring wrote:  
> >> >> On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:  
> >> >>> 1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
> >> >>> 2. QPIC NAND will 3 BAM channels: command, data tx and data rx
> >> >>>    while EBI2 NAND uses only single ADM channel.
> >> >>> 3. CRCI is only required for ADM DMA and its not required for
> >> >>>    QPIC NAND.
> >> >>>
> >> >>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
> >> >>> ---
> >> >>>  .../devicetree/bindings/mtd/qcom_nandc.txt         | 54
> >> >>> ++++++++++++++++++++--
> >> >>>  1 file changed, 51 insertions(+), 3 deletions(-)
> >> >>>
> >> >>> diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >> >>> b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >> >>> index b24adfe..8efaeb0 100644
> >> >>> --- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >> >>> +++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
> >> >>> @@ -1,13 +1,15 @@
> >> >>>  * Qualcomm NAND controller
> >> >>>
> >> >>>  Required properties:
> >> >>> -- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses
> >> >>> ADM
> >> >>> -			DMA like IPQ8064.
> >> >>> -
> >> >>> +- compatible:		must be one of the following:
> >> >>> +	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
> >> >>> +	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA
> >> >>> like IPQ4019.  
> >> >>
> >> >> Looks like you have 2 SoCs and 2 versions of h/w. Use SoC specific
> >> >> compatible strings.  
> >> >
> >> >  We have 3 versions of NAND HW currently.
> >> >  EBI2,
> >> >  QPIC version 1.4.0
> >> >  QPIC version 1.5.0
> >> >
> >> >  and multiple Qualcomm SoCs which use any one of these.
> >> >
> >> >  The original plan was to have compatible string for NAND version since
> >> >  same NAND hardware is being in different SoC and SoC dtsi will simply
> >> >  use its NAND version compatible string like other Qualcomm hardwares
> >> >
> >> >
> >> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
> >> >
> >> > http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
> >> >  
> >> 
> >>   Following are the partial list for NAND controller and supported
> >>   SoC
> >> 
> >>    EBI2:          IPQ8064, APQ8064, MSM7xx, MDM9x15
> >>    QPIC v1.4.0    MDM9x25, MDM9x35, MDM9x45, IPQ4019
> >>    QPIC v1.5.0    MDM9x55, IPQ8074
> >> 
> >>   so could we use NAND controller specific compatible strings instead 
> >> of
> >> SoC
> >>   since it will easy to maintain?  
> > 
> > Nope, though you can re-use the compatible of an old SoC for new SoCs
> > if the IP did not change.
> > 
> > For example:
> > 
> > - EBI2: compatible = "qcom,ipq8064"
> > - QPIC 1.4: compatible = "qcom,mdm9x25"
> > - QPIC 1.5: compatible = "qcom,mdm9x55"
> > 
> > Note that we usually pick the oldest SoC that started embedding an IP
> > when choosing the compatible. So my suggestion assumes IPQ8064 is older
> > than APQ8064, MSM7xx and MDM9x15.  
> 
>   Thanks Boris for detailed clarification.
>   Then I will change the patch to use SoC specific compatible string.
> 
>   Its better to use qcom,ipq4019 for 1.4.0 and qcom,ipq8074 for 1.5.0
>   since we don't have other SoC in upstream and I have tested the
>   NAND driver on these IPQ SoC's.

Sounds good, but I'll let Rob confirm.

Patch
diff mbox

diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
index b24adfe..8efaeb0 100644
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
@@ -1,13 +1,15 @@ 
 * Qualcomm NAND controller
 
 Required properties:
-- compatible:		should be "qcom,ebi2-nandc" - EBI2 NAND which uses ADM
-			DMA like IPQ8064.
-
+- compatible:		must be one of the following:
+	* "qcom,ebi2-nandc" - EBI2 NAND which uses ADM DMA like IPQ8064.
+	* "qcom,qpic-nandc-v1.4.0" - QPIC NAND v1.4.0 which uses BAM DMA like IPQ4019.
 - reg:			MMIO address range
 - clocks:		must contain core clock and always on clock
 - clock-names:		must contain "core" for the core clock and "aon" for the
 			always on clock
+
+EBI2 specific properties:
 - dmas:			DMA specifier, consisting of a phandle to the ADM DMA
 			controller node and the channel number to be used for
 			NAND. Refer to dma.txt and qcom_adm.txt for more details
@@ -18,6 +20,12 @@  Required properties:
 - qcom,data-crci:	must contain the ADM data type CRCI block instance
 			number specified for the NAND controller on the given
 			platform
+
+QPIC specific properties:
+- dmas:			DMA specifier, consisting of a phandle to the BAM DMA
+			and the channel number to be used for NAND. Refer to
+			dma.txt, qcom_bam_dma.txt for more details
+- dma-names:		must contain all 3 channel names : "tx", "rx", "cmd"
 - #address-cells:	<1> - subnodes give the chip-select number
 - #size-cells:		<0>
 
@@ -84,3 +92,43 @@  nand@1ac00000 {
 		};
 	};
 };
+
+nand@79b0000 {
+	compatible = "qcom,qpic-nandc-v1.4.0";
+	reg = <0x79b0000 0x1000>;
+
+	clocks = <&gcc GCC_QPIC_CLK>,
+		<&gcc GCC_QPIC_AHB_CLK>;
+	clock-names = "core", "aon";
+
+	dmas = <&qpicbam 0>,
+		<&qpicbam 1>,
+		<&qpicbam 2>;
+	dma-names = "tx", "rx", "cmd";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	nandcs@0 {
+		reg = <0>;
+		nand-ecc-strength = <4>;
+		nand-ecc-step-size = <512>;
+		nand-bus-width = <8>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot-nand";
+				reg = <0 0x58a0000>;
+			};
+
+			partition@58a0000 {
+				label = "fs-nand";
+				reg = <0x58a0000 0x4000000>;
+			};
+		};
+	};
+};