Patchwork [U-Boot,2/2] SPI: mxc_spi: add SPI clock calculation and setup to the driver

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Submitter Anatolij Gustschin
Date Jan. 16, 2011, 6:17 p.m.
Message ID <1295201837-26836-2-git-send-email-agust@denx.de>
Download mbox | patch
Permalink /patch/79095/
State Changes Requested
Delegated to: Stefano Babic
Headers show

Comments

Anatolij Gustschin - Jan. 16, 2011, 6:17 p.m.
The MXC SPI driver didn't calculate the SPI clock up to
now and just used lowest possible divider 512 for DATA
RATE in the control register. This results in very low
transfer rates.

The patch adds code to calculate and setup the SPI clock
frequency for transfers.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 drivers/spi/mxc_spi.c |   22 +++++++++++++++++++++-
 1 files changed, 21 insertions(+), 1 deletions(-)
Stefano Babic - Jan. 17, 2011, 9 a.m.
On 01/16/2011 07:17 PM, Anatolij Gustschin wrote:
> The MXC SPI driver didn't calculate the SPI clock up to
> now and just used lowest possible divider 512 for DATA
> RATE in the control register. This results in very low
> transfer rates.
> 

Hi August,

I sent last friday a patch for mxc_spi.c, too, adding support for mx35,
and the two patches now conflict. Is it ok for you if I rebase your
patch on top of mine and I post it again ?

Best Regards,
Stefano
Anatolij Gustschin - Jan. 17, 2011, 9:30 a.m.
Hello Stefano,

On Mon, 17 Jan 2011 10:00:51 +0100
Stefano Babic <sbabic@denx.de> wrote:

> On 01/16/2011 07:17 PM, Anatolij Gustschin wrote:
> > The MXC SPI driver didn't calculate the SPI clock up to
> > now and just used lowest possible divider 512 for DATA
> > RATE in the control register. This results in very low
> > transfer rates.
> > 
> 
> Hi August,
> 
> I sent last friday a patch for mxc_spi.c, too, adding support for mx35,
> and the two patches now conflict. Is it ok for you if I rebase your
> patch on top of mine and I post it again ?

Yes, it is ok.

Thanks,
Anatolij

--
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office@denx.de
Anatolij Gustschin - Jan. 17, 2011, 9:36 a.m.
On Mon, 17 Jan 2011 10:30:09 +0100
Anatolij Gustschin <agust@denx.de> wrote:

> Hello Stefano,
> 
> On Mon, 17 Jan 2011 10:00:51 +0100
> Stefano Babic <sbabic@denx.de> wrote:
> 
> > On 01/16/2011 07:17 PM, Anatolij Gustschin wrote:
> > > The MXC SPI driver didn't calculate the SPI clock up to
> > > now and just used lowest possible divider 512 for DATA
> > > RATE in the control register. This results in very low
> > > transfer rates.
> > > 
> > 
> > Hi August,
> > 
> > I sent last friday a patch for mxc_spi.c, too, adding support for mx35,
> > and the two patches now conflict. Is it ok for you if I rebase your
> > patch on top of mine and I post it again ?
> 
> Yes, it is ok.

BTW: While at it, could you then also please fix a mistake in the
commit description: it should be "... just highest possible divider
512".

Thanks,
Anatolij

--
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office@denx.de
Stefano Babic - Jan. 17, 2011, 9:41 a.m.
On 01/17/2011 10:36 AM, Anatolij Gustschin wrote:

> BTW: While at it, could you then also please fix a mistake in the
> commit description: it should be "... just highest possible divider
> 512".

Of course, I will do it.

Stefano

Patch

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 9ed2891..07c62c2 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -438,12 +438,25 @@  static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
 	return cs;
 }
 
+u32 get_cspi_div(u32 div)
+{
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		if (div <= (4 << i))
+			return i;
+	}
+	return i;
+}
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 			unsigned int max_hz, unsigned int mode)
 {
 	unsigned int ctrl_reg;
 	struct mxc_spi_slave *mxcs;
 	int ret;
+	u32 clk_src;
+	u32 div;
 
 	if (bus >= ARRAY_SIZE(spi_bases))
 		return NULL;
@@ -477,9 +490,16 @@  struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		return NULL;
 	}
 #else
+	clk_src = mx31_get_ipg_clk();
+	div = clk_src / max_hz;
+	div = get_cspi_div(div);
+
+	debug("clk %d Hz, div %d, real clk %d Hz\n",
+		max_hz, div, clk_src / (4 << div));
+
 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 		MXC_CSPICTRL_BITCOUNT(31) |
-		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
+		MXC_CSPICTRL_DATARATE(div) |
 		MXC_CSPICTRL_EN |
 		MXC_CSPICTRL_MODE;