@@ -2,7 +2,7 @@
SUBDIRS += hw
HW_OBJS = xscom.o chiptod.o gx.o cec.o lpc.o lpc-uart.o psi.o
HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o
-HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o
+HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o
HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o
HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o
HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o
@@ -242,6 +242,7 @@ void nx_create_compress_node(struct dt_node *node)
return;
p9_nx_enable_842(node, gcid, pb_base);
+ p9_nx_enable_gzip(node, gcid, pb_base);
} else
nx_enable_842(node, gcid, pb_base);
}
new file mode 100644
@@ -0,0 +1,127 @@
+/* Copyright 2016 IBM Corp.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ * implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <skiboot.h>
+#include <chip.h>
+#include <xscom.h>
+#include <io.h>
+#include <cpu.h>
+#include <nx.h>
+
+#define EE (1) /* enable gzip engine */
+
+static int nx_cfg_gzip_umac(struct dt_node *node, u32 gcid, u32 pb_base)
+{
+ int rc;
+ u64 umac_bar, umac_notify;
+ struct dt_node *nx_node;
+ static u32 nxgzip_tid = 1; /* tid counter within coprocessor type */
+
+ nx_node = dt_new(node, "ibm,gzip-high-fifo");
+ umac_bar = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_BAR;
+ umac_notify = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_NOTIFY_MATCH;
+
+ rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-gzip", "High", gcid,
+ NX_CT_GZIP, nxgzip_tid++, umac_bar,
+ umac_notify);
+ if (rc)
+ return rc;
+
+ nx_node = dt_new(node, "ibm,gzip-normal-fifo");
+ umac_bar = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_BAR;
+ umac_notify = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH;
+
+ rc = nx_cfg_rx_fifo(nx_node, "ibm,p9-nx-gzip", "Normal", gcid,
+ NX_CT_GZIP, nxgzip_tid++, umac_bar,
+ umac_notify);
+
+ return rc;
+}
+
+static int nx_cfg_gzip_dma(u32 gcid, u64 xcfg)
+{
+ u64 cfg;
+ int rc;
+
+ rc = xscom_read(gcid, xcfg, &cfg);
+ if (rc)
+ return rc;
+
+ cfg = SETFIELD(NX_DMA_CFG_GZIP_COMPRESS_PREFETCH, cfg,
+ DMA_COMPRESS_PREFETCH);
+ cfg = SETFIELD(NX_DMA_CFG_GZIP_DECOMPRESS_PREFETCH, cfg,
+ DMA_DECOMPRESS_PREFETCH);
+
+ cfg = SETFIELD(NX_DMA_CFG_GZIP_COMPRESS_MAX_RR, cfg,
+ DMA_COMPRESS_MAX_RR);
+ cfg = SETFIELD(NX_DMA_CFG_GZIP_DECOMPRESS_MAX_RR, cfg,
+ DMA_DECOMPRESS_MAX_RR);
+
+ rc = xscom_write(gcid, xcfg, cfg);
+ if (rc)
+ prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc);
+ else
+ prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid,
+ (unsigned long)cfg);
+
+ return rc;
+}
+
+static int nx_cfg_gzip_ee(u32 gcid, u64 xcfg)
+{
+ u64 cfg;
+ int rc;
+
+ rc = xscom_read(gcid, xcfg, &cfg);
+ if (rc)
+ return rc;
+
+ cfg = SETFIELD(NX_P9_EE_CFG_CH4, cfg, EE);
+
+ rc = xscom_write(gcid, xcfg, cfg);
+ if (rc)
+ prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc);
+ else
+ prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n",
+ gcid, (unsigned long)cfg);
+
+ return rc;
+}
+
+void p9_nx_enable_gzip(struct dt_node *node, u32 gcid, u32 pb_base)
+{
+ u64 cfg_dma, cfg_ee;
+ int rc;
+
+ prlog(PR_INFO, "NX%d: gzip at 0x%x\n", gcid, pb_base);
+
+ cfg_dma = pb_base + NX_P9_DMA_CFG;
+ cfg_ee = pb_base + NX_P9_EE_CFG;
+
+ rc = nx_cfg_gzip_dma(gcid, cfg_dma);
+ if (rc)
+ return;
+
+ rc = nx_cfg_gzip_ee(gcid, cfg_ee);
+ if (rc)
+ return;
+
+ rc = nx_cfg_gzip_umac(node, gcid, pb_base);
+ if (rc)
+ return;
+
+ prlog(PR_INFO, "NX%d: gzip Coprocessor Enabled\n", gcid);
+}
@@ -395,6 +395,7 @@ extern void nx_create_compress_node(struct dt_node *);
extern void nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base);
extern void p9_nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base);
+extern void p9_nx_enable_gzip(struct dt_node *node, u32 gcid, u32 pb_base);
extern int nx_cfg_rx_fifo(struct dt_node *node, const char *compat,
const char *priority, u32 gcid, u32 pid, u32 tid,
Power 9 introduces NX gzip compression engine. This patch adds gzip compression support in NX. Virtual Accelerator Switch (VAS) is used to access NX gzip engine and the channel configuration will be done with the receive FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used to configure RxFIFO. P9 NX supports high and normal priority FIFOS. Skiboot configures User Mode Access Control (UMAC) noitify match register with these values and also enables other registers to enable / disable the engine. Creates the following device-tree entries to provide RxFIFO address, RxFIFO size, Fifo priority, lpid, pid and tid values so that kernel can drive P9 NX gzip engine. The following nodes are located under an xscom node: /xscom@<xscom_addr>/nx@<nx_addr> /ibm,gzip-high-fifo : High priority gzip RxFIFO /ibm,gzip-normal-fifo : Normal priority gzip RxFIFO Each RxFIFO node contains: compatible : ibm,p9-nx-gzip priority : High or Normal rx-fifo-address : RxFIFO address rx-fifo-size : RxFIFO size lpid : 0xfff (1's for 12 bits in UMAC notify match register) pid : gzip coprocessor type tid : counter for gzip Signed-off-by: Haren Myneni <haren@us.ibm.com> --- hw/Makefile.inc | 2 +- hw/nx-compress.c | 1 + hw/nx-gzip.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/nx.h | 1 + 4 files changed, 130 insertions(+), 1 deletions(-) create mode 100644 hw/nx-gzip.c