From patchwork Fri Jan 14 16:08:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 78940 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id A56EBB70D5 for ; Sat, 15 Jan 2011 03:11:02 +1100 (EST) Received: (qmail 26045 invoked by alias); 14 Jan 2011 16:09:31 -0000 Received: (qmail 25840 invoked by uid 22791); 14 Jan 2011 16:09:26 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from b.mail.sonic.net (HELO b.mail.sonic.net) (64.142.19.5) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 14 Jan 2011 16:09:19 +0000 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by b.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p0EG9HSx028693 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 14 Jan 2011 08:09:17 -0800 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p0EG9HL5002080; Fri, 14 Jan 2011 08:09:17 -0800 Received: from anchor.twiddle.home (localhost.localdomain [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id p0EG9AHJ028696; Fri, 14 Jan 2011 08:09:12 -0800 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id p0EG98Gg028695; Fri, 14 Jan 2011 08:09:08 -0800 From: rth@redhat.com To: gcc-patches@gcc.gnu.org Cc: nickc@redhat.com, Richard Henderson Subject: [PATCH 07/14] rx: Implement cstoresf4. Date: Fri, 14 Jan 2011 08:08:22 -0800 Message-Id: <1295021309-28608-8-git-send-email-rth@redhat.com> In-Reply-To: <1295021309-28608-1-git-send-email-rth@redhat.com> References: <1295021309-28608-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org From: Richard Henderson --- gcc/config/rx/rx.md | 92 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 92 insertions(+), 0 deletions(-) diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md index 4ffbfec..cdae1cd 100644 --- a/gcc/config/rx/rx.md +++ b/gcc/config/rx/rx.md @@ -739,6 +739,98 @@ [(set_attr "length" "3")] ) +(define_expand "cstoresf4" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (match_operator:SI 1 "comparison_operator" + [(match_operand:SF 2 "register_operand" "") + (match_operand:SF 3 "register_operand" "")])) + (clobber (match_scratch:SI 4))])] + "ALLOW_RX_FPU_INSNS" +{ + enum rtx_code cmp1, cmp2; + + /* If the comparison needs swapping of operands, do that now. + Do not split the comparison in two yet. */ + if (rx_split_fp_compare (GET_CODE (operands[0]), &cmp1, &cmp2)) + { + rtx op2, op3; + + if (cmp2 != UNKNOWN) + { + gcc_assert (cmp1 == UNORDERED); + if (cmp2 == GT) + cmp1 = UNGT; + else if (cmp2 == LE) + cmp1 = UNLE; + else + gcc_unreachable (); + } + + op2 = operands[3]; + op3 = operands[2]; + operands[0] = gen_rtx_fmt_ee (cmp1, VOIDmode, op2, op3); + operands[2] = op2; + operands[3] = op3; + } +}) + +(define_insn_and_split "*cstoresf4" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operator:SI 4 "rx_fp_comparison_operator" + [(match_operand:SF 2 "register_operand" "r") + (match_operand:SF 3 "rx_source_operand" "rFiQ")])) + (clobber (match_scratch:SI 1 "=r"))] + "ALLOW_RX_FPU_INSNS" + "#" + "reload_completed" + [(const_int 0)] +{ + enum rtx_code cmp0, cmp1, cmp2; + rtx flags, x; + bool swap; + + cmp0 = GET_CODE (operands[4]); + swap = rx_split_fp_compare (cmp0, &cmp1, &cmp2); + gcc_assert (!swap); + + flags = gen_rtx_REG (CC_Fmode, CC_REG); + x = gen_rtx_COMPARE (CC_Fmode, operands[2], operands[3]); + x = gen_rtx_SET (VOIDmode, flags, x); + emit_insn (x); + + x = gen_rtx_fmt_ee (cmp1, SImode, flags, const0_rtx); + x = gen_rtx_SET (VOIDmode, operands[0], x); + emit_insn (x); + + if (cmp0 == LTGT) + { + /* The one case of LTGT needs to be split into ORDERED && NE. */ + x = gen_rtx_fmt_ee (EQ, VOIDmode, flags, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (SImode, x, const0_rtx, operands[0]); + x = gen_rtx_SET (VOIDmode, operands[0], x); + emit_insn (x); + } + else if (cmp2 == EQ || cmp2 == NE) + { + /* Oring the two flags can be performed with a movcc operation. */ + x = gen_rtx_fmt_ee (cmp2, VOIDmode, flags, const0_rtx); + x = gen_rtx_IF_THEN_ELSE (SImode, x, const1_rtx, operands[0]); + x = gen_rtx_SET (VOIDmode, operands[0], x); + emit_insn (x); + } + else if (cmp2 != UNKNOWN) + { + /* We can't use movcc, but need to or in another compare. + Do this by storing the second operation into the scratch. */ + x = gen_rtx_fmt_ee (cmp2, SImode, flags, const0_rtx); + x = gen_rtx_SET (VOIDmode, operands[1], x); + emit_insn (x); + + emit_insn (gen_iorsi3 (operands[0], operands[0], operands[1])); + } + DONE; +}) + (define_expand "movsicc" [(parallel [(set (match_operand:SI 0 "register_operand")