| Message ID | 1500293043-1887-3-git-send-email-varada@codeaurora.org |
|---|---|
| State | Superseded |
| Headers | show |
On Mon, Jul 17, 2017 at 05:33:58PM +0530, Varadarajan Narayanan wrote: > IPQ8074 uses QMP phy controller that provides support to PCIe and > USB. Adding dt binding information for the same. > > Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> > --- > .../devicetree/bindings/phy/qcom-qmp-phy.txt | 28 ++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > index 5d7a51f..80d766b 100644 > --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > @@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. > > Required properties: > - compatible: compatible list, contains: > + "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 > "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, > "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. > > @@ -107,3 +108,30 @@ Example: > ... > ... > }; > + > + phy@86000 { Only a new compatible doesn't warrant another example. Rob
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 5d7a51f..80d766b 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. Required properties: - compatible: compatible list, contains: + "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. @@ -107,3 +108,30 @@ Example: ... ... }; + + phy@86000 { + compatible = "qcom,ipq8074-qmp-pcie-phy"; + reg = <0x86000 0x1000>; + + #clock-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + status = "ok"; + + pciephy_0: lane@86000 { + reg = <0x86200 0x130>, + <0x86400 0x200>, + <0x86800 0x1f8>; + #phy-cells = <0>; + clocks = <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "pcie20_phy0_pipe_clk"; + }; + };
IPQ8074 uses QMP phy controller that provides support to PCIe and USB. Adding dt binding information for the same. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> --- .../devicetree/bindings/phy/qcom-qmp-phy.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+)