Patchwork [04/14] rx: Split cstoresi4 post-reload.

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Submitter Richard Henderson
Date Jan. 14, 2011, 4:08 p.m.
Message ID <1295021309-28608-5-git-send-email-rth@redhat.com>
Download mbox | patch
Permalink /patch/78936/
State New
Headers show

Comments

Richard Henderson - Jan. 14, 2011, 4:08 p.m.
From: Richard Henderson <rth@twiddle.net>

This will allow elimination of the compare.
---
 gcc/config/rx/rx.c  |    2 --
 gcc/config/rx/rx.h  |    2 --
 gcc/config/rx/rx.md |   41 +++++++++++++++++++++++++++++------------
 3 files changed, 29 insertions(+), 16 deletions(-)

Patch

diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index a2ff95e..992c585 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -363,8 +363,6 @@  rx_assemble_integer (rtx x, unsigned int size, int is_aligned)
 }
 
 
-int rx_float_compare_mode;
-
 /* Handles the insertion of a single operand into the assembler output.
    The %<letter> directives supported are:
 
diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h
index d26c80c..e2c8641 100644
--- a/gcc/config/rx/rx.h
+++ b/gcc/config/rx/rx.h
@@ -595,8 +595,6 @@  typedef unsigned int CUMULATIVE_ARGS;
    they contain are always computed between two same-section symbols.  */
 #define JUMP_TABLES_IN_TEXT_SECTION	(flag_pic)
 
-extern int rx_float_compare_mode;
-
 /* This is a version of REG_P that also returns TRUE for SUBREGs.  */
 #define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
 
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index c2161a2..f9a7c02 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -706,20 +706,37 @@ 
    (set_attr "timings" "45")] ;; The timing is a guesstimate average timing.
 )
 
-;; FIXME: Add memory destination options ?
-(define_insn "cstoresi4"
-  [(set (match_operand:SI   0 "register_operand" "=r,r,r,r,r,r,r")
+(define_insn_and_split "cstoresi4"
+  [(set (match_operand:SI   0 "register_operand" "=r")
 	(match_operator:SI  1 "comparison_operator"
-	 [(match_operand:SI 2 "register_operand"  "r,r,r,r,r,r,r")
-	  (match_operand:SI 3 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")]))
-   (clobber (reg:CC CC_REG))] ;; Because the cc flags are set based on comparing ops 2 & 3 not the value in op 0.
+	  [(match_operand:SI 2 "register_operand"  "r")
+	   (match_operand:SI 3 "rx_source_operand" "riQ")]))
+   (clobber (reg:CC CC_REG))]
   ""
-  {
-    rx_float_compare_mode = false;
-    return "cmp\t%Q3, %Q2\n\tsc%B1.L\t%0";
-  }
-  [(set_attr "timings" "22,22,22,22,22,22,44")
-   (set_attr "length"  "5,5,6,7,8,9,8")]
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+{
+  rtx flags, x;
+
+  flags = gen_rtx_REG (CCmode, CC_REG);
+  x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
+  x = gen_rtx_SET (VOIDmode, flags, x);
+  emit_insn (x);
+
+  x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
+  x = gen_rtx_SET (VOIDmode, operands[0], x);
+  emit_insn (x);
+  DONE;
+})
+
+(define_insn "*sccc"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operator:SI 1 "comparison_operator"
+	  [(reg CC_REG) (const_int 0)]))]
+  "reload_completed"
+  "sc%B1.L\t%0"
+  [(set_attr "length" "3")]
 )
 
 (define_expand "movsicc"